IBM0117805 IBM0117805M
IBM0117805B IBM0117805P
2M x 8 11/10 EDO DRAM
Self Refresh Cycle (Sleep Mode) - Low Power version only
tRASS
tRPS
VIH
RAS
VIL
tRPC
tCHS
tCSR
tCRP
tCP
tCHD
VIH
VIL
CAS
WE
tWRH
tWRP
VIH
VIL
tOFF
VOH
VOL
DOUT
Hi-Z
: “H” or “L”
NOTES:
1. Address and OE are “H” or “L”
2. Once RAS (min) is provided and RAS remains low, the DRAM
will be in Self Refresh, commonly known as “Sleep Mode.”
3. If tRASS > tCHD (min) then tCHD applies.
If tRASS ≤ tCHD (min) then tCHS applies.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4724
SA14-4221-04
Revised 11/96
Page 27 of 29
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