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IBM0116405MT1-50 参数 Datasheet PDF下载

IBM0116405MT1-50图片预览
型号: IBM0116405MT1-50
PDF下载: 下载PDF文件 查看货源
内容描述: [EDO DRAM, 4MX4, 50ns, CMOS, PDSO24, 0.300 X 0.675 INCH, TSOP2-26/24]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 31 页 / 373 K
品牌: IBM [ IBM ]
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Discontinued (9/98 - last order; 3/99 last ship)  
IBM0116405  
IBM0116405M  
IBM0116405B IBM0116405P  
4M x 4 12/10 EDO DRAM  
Write Cycle  
-50  
-60  
Symbol  
Parameter  
Units  
Notes  
1
Min.  
0
Max.  
Min.  
0
Max.  
tWCS  
tWCH  
tWP  
Write Command Set Up Time  
Write Command Hold Time  
Write Command Pulse Width  
Write Command to RAS Lead Time  
Write Command to CAS Lead Time  
OE to DIN Delay Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
7
10  
10  
10  
10  
15  
0
7
tRWL  
tCWL  
tOED  
tDS  
7
7
13  
0
2
3
3
DIN Setup Time  
tDH  
DIN Hold Time  
7
10  
1. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics  
only. If tWCS tWCS (min), the cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the  
entire cycle. If tRWD tRWD (min), tCWD tCWD (min) and tAWD tAWD (min), the cycle is a Read-Modify-Write cycle and the data out  
will contain data read from the selected cell. If neither of the above sets of conditions are satisfied, the condition of the data out (at  
access time) is indeterminate.  
2. Either tCDD or tOED must be satisfied.  
3. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in Read-Modify-Write cycles.  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
28H4720  
SA14-4226-06  
Revised 4/97  
 
 
 
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