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HY5DU283222BFP 参数 Datasheet PDF下载

HY5DU283222BFP图片预览
型号: HY5DU283222BFP
PDF下载: 下载PDF文件 查看货源
内容描述: 128M ( 4Mx32 ) GDDR SDRAM [128M(4Mx32) GDDR SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 30 页 / 262 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
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1HY5DU283222BF(P)  
DESCRIPTION  
The Hynix HY5DU283222 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the  
point-to-point applications which requires high bandwidth.  
The Hynix 4Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the  
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,  
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-  
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible  
with SSTL_2.  
FEATURES  
The Hynix HY5DU283222BF(P) guarantee until  
200MHz speed at DLL_off condition  
rising and falling edges of the data strobe  
All addresses and control inputs except Data, Data  
strobes and Data masks latched on the rising edges  
of the clock  
2.5V VDD and VDDQ wide range max power supply  
supports  
All inputs and outputs are compatible with SSTL_2  
interface  
Write mask byte controls by DM (DM0 ~ DM3)  
Programmable /CAS Latency 5 / 4 / 3 supported  
12mm x 12mm, 144ball FBGA with 0.8mm pin pitch  
Fully differential clock inputs (CK, /CK) operation  
Double data rate interface  
Programmable Burst Length 2 / 4 / 8 with both  
sequential and interleave mode  
Internal 4 bank operations with single pulsed /RAS  
tRAS Lock-Out function supported  
Source synchronous - data transaction aligned to  
bidirectional data strobe (DQS0 ~ DQS3)  
Auto refresh and self refresh supported  
4096 refresh cycles / 32ms  
Data outputs on DQS edges when read (edged DQ)  
Data inputs on DQS centers when write (centered  
DQ)  
Half strength and Matched Impedance driver option  
controlled by EMRS  
Data(DQ) and Write masks(DM) latched on the both  
ORDERING INFORMATION  
Clock  
Frequency  
Part No.  
Power Supply  
Max Data Rate  
interface  
Package  
HY5DU283222BF(P)-2  
HY5DU283222BF(P)-22  
HY5DU283222BF(P)-25  
HY5DU283222BF(P)-28  
HY5DU283222BF(P)-33  
HY5DU283222BF(P)-36  
HY5DU283222BF(P)-4  
HY5DU283222BF(P)-5  
500MHz  
450MHz  
400MHz  
350MHz  
300MHz  
275MHz  
250MHz  
200MHz  
1000Mbps/pin  
900Mbps/pin  
800Mbps/pin  
700Mbps/pin  
600Mbps/pin  
550Mbps/pin  
500Mbps/pin  
400Mbps/pin  
VDD/ VDDQ = 2.5V  
12mm x 12mm  
144Ball FBGA  
SSTL_2  
Note) Hynix supports Lead free parts for each speed grade with same specification, except Lead free materials.  
We'll add "P" character after "F" for Lead free product.  
For example, the part number of 300MHz Lead free product is HY5DU283222BFP-33.  
Rev. 1.2 / Jul. 2005  
3