1HY5DU283222BF(P)
Revision History
No.
History
Draft Date
Jun. 2004
Jun. 2004
Remark
0.1
0.2
1) Defined Target Spec.
1) Added 200MHz speed bin
1) Changed Cas Latency to 4 clock from 5 clock at 300Mhz/275Mhz/
0.3
0.4
1.0
Sep. 2004
Oct. 2004
Feb. 2005
250Mhz speed bin
1) Changed IDD & 500Mhz speed bin insert,
2) Changed tRCDWR, tWR at 450Mhz speed bin
1) Changed IDD Spec.
2) Changed CAS Latency to 4 clock from 5 clock at 350MHz speed bin
1.1
1.2
May. 2005
Jul. 2005
tWR/ tDAL Changed at 200Mhz
IDD6 change
Rev. 1.2 / Jul. 2005
2