HY5DU281622ET
MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,
burst type, test mode, DLL reset. The mode register is program via MRS command. This command is issued by the low
signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and CKE
must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to write
the data in mode register. During the the MRS cycle, any command cannot be issued. Once mode register field is
determined, the information will be held until resetted by another MRS command.
BA1 BA0 A11 A10
A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
0
0
RFU*
DR
TM
CAS Latency
Burst Length
BA0
0
MRS Type
A7
0
Test Mode
MRS
Normal
1
EMRS
Vendor
test mode
1
Burst Length
A2
A1
A0
A8
0
DLL Reset
No
Sequential
Interleave
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
2
1
Yes
4
4
8
8
A6
0
A5
0
A4
0
CAS Latency
Reserved
Reserved
Reserved
3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
1
0
1
0
0
1
1
1
0
0
4
A3
0
Burst Type
Sequential
Interleave
1
0
1
5
1
1
0
Reserved
Reserved
1
1
1
1
* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage.
And, if MRS/EMRS are programmed with ‘Reserved’ code, it could be the cause of mal-function.
Rev. 0.5 / Jan. 2005
17
HYNIX [ HYNIX SEMICONDUCTOR ]
