Synchronous DRAM Memory 64Mbit (4Mx16bit)
HY57V641620F(L/S)TP Series
PIN DESCRIPTION
SYMBOL
CLK
TYPE
Clock
DESCRIPTION
The system clock input. All other inputs are registered to the
SDRAM on the rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE, UDQM and LDQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA7
Auto-precharge flag: A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write
mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
CKE
CS
BA0, BA1
Clock Enable
Chip Select
Bank Address
A0 ~ A11
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input / Output
Power Supply / Ground
Data Output Power /
Ground
No Connection
RAS, CAS, WE
UDQM, LDQM
DQ0 ~ DQ15
VDD / VSS
VDDQ / VSSQ
NC
Rev. 1.0 / Apr. 2007
4