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HY29F002TT-55 参数 Datasheet PDF下载

HY29F002TT-55图片预览
型号: HY29F002TT-55
PDF下载: 下载PDF文件 查看货源
内容描述: 2兆位( 256K ×8 ) , 5伏只,闪存 [2 Megabit (256K x 8), 5 Volt-only, Flash Memory]
分类和应用: 闪存
文件页数/大小: 38 页 / 381 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
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HY29F002T  
START  
START  
Issue PROGRAM  
Command Sequence:  
Last cycle contains  
Issue CHIP ERASE  
Command Sequence  
program Address/Data  
Check Erase Status  
(See Write Operation Status  
Section)  
Check Programming Status  
(See Write Operation Status  
Section)  
DQ[5] Error Exit  
DQ[5] Error Exit  
Normal Exit  
Normal Exit  
GO TO  
ERROR RECOVERY  
CHIP ERASE COMPLETE  
NO  
Last Word/Byte  
Done?  
Figure 5. Chip Erase Procedure  
YES  
mine the status of the erase operation, as de-  
scribed in the Write Operation Status section.  
PROGRAMMING  
COMPLETE  
GO TO  
ERROR RECOVERY  
Figure 5 illustrates the Chip Erase procedure.  
Figure 4. Programming Procedure  
this state, and a succeeding read will show that  
Sector Erase Command  
the data is still 0.  
The Sector Erase command sequence consists  
of two unlock cycles, followed by the erase com-  
mand, two additional unlock cycles and then the  
sector erase data cycle, which specifies which  
sector is to be erased. As described later in this  
section, multiple sectors can be specified for era-  
sure with a single command sequence. During  
sector erase, all specified sectors are erased se-  
quentially. The data in sectors not specified for  
erasure, as well as the data in any protected sec-  
tors specified for erasure, is not affected by the  
sector erase operation.  
Figure 4 illustrates the procedure for the Program  
operation.  
Chip Erase Command  
The Chip Erase command sequence consists of  
two unlock cycles, followed by the erase command,  
two additional unlock cycles and then the chip erase  
data cycle. During chip erase, all sectors of the  
device are erased except protected sectors. The  
command sequence starts the Automatic Erase al-  
gorithm, which preprograms and verifies the entire  
memory, except for protected sectors, for an all zero  
data pattern prior to electrical erase. The device  
then provides the required number of internally  
generated erase pulses and verifies cell erasure  
within the proper cell margins. The host system is  
not required to provide any controls or timings dur-  
ing these operations.  
The Sector Erase command sequence starts the  
Automatic Erase algorithm, which preprograms  
and verifies the specified unprotected sectors for  
an all zero data pattern prior to electrical erase.  
The device then provides the required number of  
internally generated erase pulses and verifies cell  
erasure within the proper cell margins. The host  
system is not required to provide any controls or  
timings during these operations.  
Commands written to the device during execution  
of the Automatic Erase algorithm are ignored. Note  
that a hardware reset immediately terminates the  
erase operation. To ensure data integrity, the  
aborted chip erase command sequence should be  
reissued once the reset operation is complete.  
After the sector erase data cycle (the sixth bus  
cycle) of the command sequence is issued, a sec-  
tor erase time-out of 50 µs (minimum), measured  
from the rising edge of the final WE# pulse in that  
bus cycle, begins. During this time, an additional  
sector erase data cycle, specifying the sector ad-  
dress of another sector to be erased, may be writ-  
ten into an internal sector erase buffer. This buffer  
When the Automatic Erase algorithm is finished,  
the device returns to the Read mode. Several  
methods are provided to allow the host to deter-  
Rev. 4.1/May 01  
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