HL15604
ii )SCK is stopped at the high level
CE
SCK
SI
XX
XX
XX
XX
0
1
0
0
0
0
1
0
D2 D3
D1
D41
D42 D43 D44
0
0
0
0
0
0
0
0
S0 S1 K0 K1 P0 P1 SC DR
Control data
0
0
1
1
0
1
0
1
A0 A1 A2 A3 A4 A5 A6
A7
Display data
DD
DD
DD
DD
SO
CE
SCK
SI
0
1
0
0
0
0
1
0
D46
D45
D83
D84
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A0 A1 A2 A3 A4 A5 A6
A7
Display data
Fixed data
SO
CE
SCK
SI
D123
D124
0
1
0
0
0
0
1
0
D86
D85
0
0
0
0
A0 A1 A2 A3 A4 A5 A6
A7
Display data
Fixed data
SO
CE
SCK
SI
D163
D164
0
1
0
0
0
0
1
0
D125D126
0
0
0
0
A0 A1 A2 A3 A4 A5 A6
A7
Display data
Fixed data
SO
A7~A0 : 42H address
D164~D1 : Data of LCD display registers
S0, S1 : Sleep control data
K0, K1 : Key scan output / Segment output selection data
P0, P1 : Segment output / general-purpose output port selection data
SC
DR
: Segment on / off control data
: 1/2 bias or 1/3 bias drive selection data
8
HYNIX [ HYNIX SEMICONDUCTOR ]
