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1Gbit (32Mx32bit) Mobile SDR Memory
H55S1G(2/3)2MFP Series
READ
A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1)
cycle after read command set. The SDRAM can perform a burst read operation.
The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address and
the bank select address at the read command set cycle. In a read operation, data output starts after the number of
clocks specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3.
When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the suc-
cessive burst-length data has been output.
The /CAS latency and burst length must be specified at the mode register.
tCK
CLK
REA
D
Command
DQ
NOP
NOP
tOH
Do0
tLZ
Do1
Do2
Do3
tAC
CL = 2
REA
D
NOP
NOP
NOP
tOH
Do0
Command
tLZ
Do1
Do2
Do3
DQ
tAC
Undefined
Don't Care
CL = 3
Read Burst Showing CAS Latency
Rev 1.2 / Jun. 2008
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HYNIX [ HYNIX SEMICONDUCTOR ]
