GMS90 Series
Pin Number
Input/
Symbol
Function
PLCC-
44
PDIP-
40
MQFP-
44
Output
XTAL1
XTAL1
21
19
15
I
Input to the inverting oscillator amplifier and input to
the internal clock generator circuits.To drive the
device from an external clock source, XTAL1 should
be driven, while XTAL2 is left unconnected. There are
no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking
circuitry is divided down by a divide-by-two flip-flop.
Minimum and maximum high and low times as well as
rise fall times specified in the AC characteristics must
be observed.
Port 2
P2.0-P2.7
24-31
21-28
18-25
I/O
Port 2 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 2 pins that have 1s written to them are
pulled high by the internal pull-up resistors and can be
used as inputs. As inputs, port 2 pins that are
externally pulled low will source current because of
the pulls-ups (IIL, in the DC characteristics).Port 2
emits the high-order address byte during fetches from
external program memory and during accesses to
external data memory that use 16-bit addresses
(MOVX @DPTR). In this application it uses strong
internal pull-ups when emitting 1s. During accesses to
external data memory that use 8-bit addresses
(MOVX @Ri), port 2 emits the contents of the P2
special function register.
The Program Store Enable
PSEN
32
29
26
O
The read strobe to external program memory when
the device is executing code from the external
program memory. PSEN is activated twice each
machine cycle, except that two PSEN activations are
skipped during each access to external data memory.
PSEN is not activated during fetches from internal
program memory.
RESET
RESET
10
9
4
I
A high level on this pin for two machine cycles while
the oscillator is running resets the device. An internal
diffused resistor to VSS permits power-on reset using
only an external capacitor to VCC
.
Dec. 1998 Ver 3.0
9
HYNIX [ HYNIX SEMICONDUCTOR ]
