GMS90 Series
HYUNDAI MicroElectronics
ALE
t
LHLL
t
WHLH
PSEN
RD
t
LLDV
t
t
RLRH
LLWL
t
RHDZ
t
AVLL
t
RLDV
t
t
LLAX2
t
RHDX
DATA IN
RLAZ
A0-A7 from
RI or DPL
A0-A7 from PCL
INSTR. IN
PORT 0
PORT 2
t
AVWL
t
AVDV
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
Figure 5. External Data Memory Read Cycle
ALE
t
LHLL
t
WHLH
PSEN
WR
t
t
WLWH
LLWL
t
QVWX
t
t
WHQX
AVLL
t
LLAX2
t
QVWH
A0-A7 from
RI or DPL
A0-A7 from PCL
DATA OUT
INSTR. IN
PORT 0
PORT 2
t
AVWL
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
Figure 6. External Data Memory Write Cycle
Oct. 2000 Ver 3.1a
43