Hyundai Micro Electronics
GMS81C2020/GMS81C2120
timer register T0 (T1) increases and matches TDR0
(TDR1).
tured into registers CDRx (CDR0, CDR1), respectively.
After captured, Timer x register is cleared and restarts by
hardware.
This timer interrupt in capture mode is very useful when
the pulse width of captured signal is more wider than the
maximum period of Timer.
It has three transition modes: "falling edge", "rising edge",
"both edge" which are selected by interrupt edge selection
register IEDS (Refer to External interrupt section). In ad-
dition, the transition at INTx pin generate an interrupt.
For example, in Figure 15-8 , the pulse width of captured
signal is wider than the timer data value (FFH) over 2
times. When external interrupt is occured, the captured
value (13H) is more little than wanted value. It can be ob-
tained correct value by counting the number of timer over-
flow occurence.
Note: The CDRx, TDRx and Tx are in same address. In
the capture mode, reading operation is read the
CDRx, not Tx because path is opened to the CDRx,
and TDRx is only for writing operation.
Timer/Counter still does the above, but with the added fea-
ture that a edge transition at external input INTx pin causes
the current value in the Timer x register (T0,T1), to be cap-
ADDRESS : D0H
RESET VALUE : --000000
-
-
CAP0
1
T0CK2
X
T0CK1
X
T0CK0
X
T0CN
X
T0ST
X
TM0
TM1
-
-
ADDRESS : D2H
RESET VALUE : 00000000
POL
X
16BIT
0
PWM1E
0
CAP1
1
T1CK1
X
T1CK0
X
T1CN
X
T1ST
X
T0CK[2:0]
T0ST
0 : Stop
1 : Clear and Start
Edge Detector
1
T0CK
CLEAR
EC0
T0 ( 8-bit )
MUX
2
÷
4
÷
TIMER 0
INTERRUPT
CAPTURE
T0IF
8
÷
T0CN
COMPARATOR
32
÷
fXI
128
÷
CDR0 ( 8-bit )
TDR0 ( 8-bit )
512
÷
2048
÷
INT 0
INTERRUPT
INT0IF
INT0
T0ST
0 : Stop
1 : Clear and Start
IEDS[1:0]
1
1
÷
MUX
CLEAR
T1 ( 8-bit )
2
÷
8
÷
TIMER 1
INTERRUPT
CAPTURE
T1IF
COMPARATOR
T1CN
T1CK[1:0]
IEDS[3:2]
CDR1 ( 8-bit )
TDR1 ( 8-bit )
INT 1
INTERRUPT
INT1IF
INT1
Figure 15-6 8-bit Capture Mode
Nov. 1999 Ver 0.0
preliminary
55
HYNIX [ HYNIX SEMICONDUCTOR ]
