Hyundai Micro Electronics
GMS81C2020/GMS81C2120
11.3 Data Memory (GMS81C2020)
Figure 11-7 shows the internal Data Memory space avail-
able. Data Memory is divided into two groups, a user
RAM(including Stack) and control registers.
RESET
Value
Addressing
mode
Symbol
R/W
Address
0C0H
0C1H
0C2H
0C3H
0C4H
0C5H
0C6H
0C7H
0C8H
0C9H
0CAH
0CBH
0CCH
0CDH
0CEH
0CFH
R0
R0IO
R1
R1IO
R2
R/W Undefined byte, bit1
byte2
byte, bit
byte
byte, bit
byte
byte, bit
byte
0000H
W
0000_0000
R/W Undefined
00000000
R/W Undefined
0000_0000
R/W Undefined
--00_0000
R/W Undefined
----_0000
R/W Undefined
0000_0000
R/W Undefined
0000_0000
R/W Undefined
----_0000
W
USER
MEMORY
R2IO
R3
W
PAGE0
00BFH
R3IO
R4
W
00C0H
CONTROL
byte, bit
byte
REGISTERS
R4IO
R5
W
00FFH
byte, bit
byte
0100H
R5IO
R6
W
USER
MEMORY
byte, bit
byte
PAGE1
R6IO
R7
R7IO
W
( including STACK )
byte, bit
byte
01FFH
W
0D0H
0D1H
0D1H
0D1H
0D2H
0D3H
0D3H
0D4H
0D4H
0D4H
0D5H
0DEH
TM0
T0
TDR0
CDR0
TM1
TDR1
T1PPR
T1
CDR1
T1PDR
PWM1HR
BUR
R/W --00_0000
byte, bit
byte
R
W
R
0000_0000
1111_1111
0000_0000
byte
Figure 11-7 Data Memory Map
User Memory
byte
R/W 0000_0000
byte, bit
byte
W
W
R
1111_1111
1111_1111
0000_0000
0000_0000
byte
The GMS81C2020 has 448 × 8 bits for the user memory
(RAM).
byte
R
byte
R/W 0000_0000
W
W
byte, bit
byte
----_0000
1111_1111
Control Registers
byte
The control registers are used by the CPU and Peripheral
function blocks for controlling the desired operation of the
device. Therefore these registers contain control and status
bits for the interrupt system, the timer/ counters, analog to
digital converter, basic interval timer, serial peripheral in-
terface, watchdog timer, buzzer driver and I/O ports. The
control registers are in address range of 0C0H to 0FFH.
0E0H
0E1H
0E2H
0E3H
0E4H
0E5H
0E6H
0EAH
0EBH
0ECH
0ECH
0EDH
0EDH
0EFH
SIOM
SIOR
R/W 0000_0001
R/W Undefined
R/W 0000_----
R/W 0000_----
R/W 0000_----
R/W 0000_----
R/W ----_0000
R/W -000_0001
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte
IENH
IENL
IRQH
IRQL
IEDS
ADCM
ADCR
BITR
R
R
Undefined
0000_0000
-001_0111
0000_0000
0111_1111
Note that unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in gen-
eral return random data, and write accesses will have an in-
determinate effect.
byte
CKCTLR
WDTR
WDTR
PFDR
W
R
byte
byte
W
byte
R/W ----_-100
byte, bit
0F4H
0F5H
0F6H
0F7H
0F8H
0F9H
0FAH
0FBH
R0FUNC
R4FUNC
R5FUNC
R6FUNC
R7FUNC
R5NODR
SCMR
W
W
W
W
W
W
----_0000
----_--00
0000_0000
0000_0000
----_0000
0000_0000
byte
byte
byte
byte
byte
byte
byte
-
More detailed informations of each register are explained
in each peripheral section.
Note: Write only registers can not be accessed by bit ma-
nipulation instruction. Do not use read-modify-write
instruction. Use byte manipulation instruction.
R/W ---0_0000
Undefined
RA
R
Table 11-1 Control Registers
1. "byte, bit" means that register can be addressed by not only bit
but byte manipulation instruction.
Example; To write at CKCTLR
2. "byte" means that register can be addressed by only byte
manipulation instruction. On the other hand, do not use any
read-modify-write instruction such as bit manipulation for
clearing bit.
LDM
CKCTLR,#09H;Divide ratio ÷16
Note: Several names are given at same address. Refer to
Nov. 1999 Ver 0.0
preliminary
31
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