Hyundai Micro Electronics
GMS81C2020/GMS81C2120
MSB
N
LSB
C
V
G
B
H
I
Z
[RESET VALUE : 00
PSW
NEGATIVE FLAG
H
CARRY FLAG RECEIVES
CARRY OUT
OVERFLOW FLAG
ZERO FLAG
DIRECT PAGE FLAG
INTERRUPT ENABLE FLAG
BREAK FLAG
HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS
Figure 11-3 PSW (Program Status Word) Register
This flag assign direct page(0-page, 1-page) for direct ad-
[Interrupt disable flag I]
dressing mode. When G-flag is "0", the direct addressing
space is in 0-page(0000h ~ 00FFH). When G-flag is "1",
the direct addressing space is in 1-page(0100h ~ 01FFH).
It is set and clreared by SETG, CLRG instruction.
This flag enables/disables all interrupts except interrupt
caused by Reset or software BRK instruction. All inter-
rupts are disabled when cleared to "0". This flag immedi-
ately becomes "0" when an interrupt is served. It is set by
the EI instruction and cleared by the DI instruction.
[Overflow flag V]
[Half carry flag H]
This flag is set to "1" when an overflow occurs as the result
of an arithmetic operation involving signs. An overflow
occurs when the result of an addition or subtraction ex-
ceeds +127(7FH) or -128(80H). The CLRV instruction
clears the overflow flag. There is no set instruction. When
the BIT instruction is executed, bit 6 of memory is copied
to this flag.
After operation, this is set when there is a carry from bit 3
of ALU or there is no borrow from bit 4 of ALU. This bit
can not be set or cleared except CLRV instruction with
Overflow flag (V).
[Break flag B]
This flag is set by software BRK instruction to distinguish
BRK from TCALL instruction with the same vector ad-
dress
[Negative flag N]
This flag is set to match the sign bit (bit 7) status of the re-
sult of a data or arithmetic operation. When the BIT in-
struction is executed, bit 7 of memory is copied to this flag.
[Direct Page flag G]
Nov. 1999 Ver 0.0
preliminary
27
HYNIX [ HYNIX SEMICONDUCTOR ]
