GMS81C5108
23. SUPPLY VOLTAGE DETECTION
The GMS81C5108 has an on-chip low voltage detection
circuitry to detect the VDD voltage. A configuration regis-
ter, SCMR, can enable or disable the low voltage detect
circuitry. This GMS81C5108 has two level detec-
tor(SVD0, SVD1). The SVD0 flag is set when the VDD
falls below 2.2V and if the VDD is rise above 2.2V the
SVD0 is cleared automatically. The SVD1 flag is set when
the VDD falls below 1.7V and if this flag is set once, it is
not cleared automatically although the VDD rises above
1.7V. It can be cleared by writing.
If the SVD1 is set, the MCU can be RESET or frozen by
the flag SVRT. In the in-circuit emulator, supply voltage
detection is not implemented and user can not experiment
with it. Therefore, after final development of user program,
this function may be experimented or evaluated.
MSB
LSB
R/W R/W R/W
R
R/W R/W R/W R/W
SCMR (System
Clock Mode Register)
ADDRESS: 0F5
INITIAL VALUE: 00
H
H
SYCC[1:0] (System clock control)
00: main clock on
01: main clock on
10: sub clock on (main clock on)
11: sub clock on (main clock off)
SCS[1:0] (System clock source select)
or fSUB÷2
or fSUB÷2
f
f
f
f
MAIN÷2
MAIN÷2
SVD[1:0] (SVD Flag)
SVD0 : set at VDD=2.2V
SVD1 : set at VDD=1.7V
3
4
6
3
4
MAIN÷2 or fSUB÷2
6
MAIN÷2 or fSUB÷2
SVRT (System Reset Control by SVD1 Bit)
0 : System reset by SVD1 Flag
1 : Don’t system reset by SVD1 Flag (Freeze)
SVEN (SVD Operation Enable Bit)
0 : SVD Operation Enable
1 : SVD Operation Disable
* The values of 1.7V and 2.2V could be changed by ±0.2V according to the process of work.
Figure 23-1 Low Voltage Detector Register
V
DD
SVD MAX
SVD MIN
65.5mS
Internal
RESET
V
DD
SVD MAX
SVD MIN
When SVRT = 0
65.5mS
65.5mS
Internal
RESET
t < 65.5mS
V
DD
SVD MAX
SVD MIN
Internal
RESET
V
DD
SVD MAX
SVD MIN
System
Clock
When SVRT = 1
V
DD
SVD MAX
SVD MIN
System
Clock
Figure 23-2 Power Fail Processor Situations
82
JUNE 2001 Ver 1.0
HYNIX [ HYNIX SEMICONDUCTOR ]
