GMS81C5108
22. RESET
The GMS81C5108 have two types of reset generation pro-
cedures; one is an external reset input, the other is a watch-
dog timer reset. Table 22-1 shows on-chip hardware ini-
tialization by reset action.
On-chip Hardware
Initial Value
On-chip Hardware
Peripheral clock
Initial Value
(FFFFH) - (FFFEH)
Program counter
(PC)
(RPR)
(G)
On
Enable
RAM page register
G-flag
0
SVD
0
Control registers
Voltage Booster
Refer to Table 8-1 on page 25
Disable
Operation mode
Main-frequency clock
Table 22-1 Initializing Internal Status by Reset Action
22.1 External Reset Input
The reset input is the RESET pin, which is the input to a
Schmitt Trigger. A reset in accomplished by holding the
RESET pin to low for at least 8 oscillator periods, within
the operating voltage range and oscillation stable, it is ap-
plied, and the internal state is initialized. After reset,
65.5ms (at 4MHz) add with 7 oscillator periods are re-
quired to start execution as shown in Figure 22-2.
A connection for simple power-on-reset is shown in Figure
22-1.
V
DD
V
DD
100kΩ
Mask Option
RESET
Internal RAM is not affected by reset. When VDD is turned
on, the RAM content is indeterminate. Therefore, this
RAM should be initialized before read or tested it.
+
1uF
−
MCU
GND
When the RESET pin input goes to high, the reset opera-
tion is released and the program execution starts at the vec-
tor address stored at FFFEH - FFFFH.
Figure 22-1 Simple Power-on-Reset Circuit
1
2
3
4
5
6
7
System Clock
RESET
ADDRESS
FFFE FFFF Start
?
?
?
?
BUS
DATA
BUS
OP
?
ADH
FE
ADL
?
?
?
MAIN PROGRAM
RESET Process Step
1
Stabilization Time
= 65.5mS at 4MHz
t
ST
t
=
x 256
ST
f
÷1024
MAIN
Figure 22-2 Timing Diagram after RESET
22.2 Watchdog Timer Reset
Refer to “13.2 Watch Dog Timer” on page 57.
JUNE 2001 Ver 1.0
81
HYNIX [ HYNIX SEMICONDUCTOR ]
