GMS81C5108
6. PORT STRUCTURES
R00~R03/INT0~INT2, R03/EC0, R07/SI
R10~R17/KS0~KS7
Pull up
Reg.
Pull up
Reg.
Pull-up Tr.
Pull-up Tr.
Open Drain
Open Drain
Reg.
Reg.
V
DD
V
DD
Data Reg.
Data Reg.
Pin
Pin
Dir. Reg.
Dir. Reg.
PMR<0:3,7>
KSMR<0:7>
V
SS
V
SS
M U X
M U X
RD
RD
RD
RD
INT0 ~ INT2
Noise
Canceller
EC0,SI
Key Scan
Noise
Canceller
KS0 ~ KS7
Key Scan
Enable
R04/BUZ, R06/SO
Pull up
Reg.
Pull-up Tr.
R20~R23/AN0~AN3
V
DD
Open Drain
Reg.
Pull up
Reg.
Pull-up Tr.
Data Reg.
BUZ,SO
Open Drain
Reg.
V
DD
Dir. Reg.
Data Reg.
Dir. Reg.
Pin
V
SS
Pin
M U X
RD
V
RD
SS
M U X
R05/SCK
RD
RD
Pull up
Reg.
Pull-up Tr.
A/D converter
AN0 ~ AN3
V
DD
Open Drain
Reg.
A/D Enable
channel select
Data Reg.
SCK(OUT)
Dir. Reg.
Pin
SCK(IN)_EN
V
SS
M U X
RD
RD
Noise
Canceller
SCK(IN)
8
JUNE 2001 Ver 1.0
HYNIX [ HYNIX SEMICONDUCTOR ]
