HYUNDAI MicroElectronics
16.3 Multi Interrupt
GMS81C2012/GMS81C2020
If two requests of different priority levels are received si-
multaneously, the request of higher priority level is ser-
viced. If requests of the interrupt are received at the same
time simultaneously, an internal polling sequence deter-
mines by hardware which request is serviced.
However, multiple processing through software for special
features is possible. Generally when an interrupt is accept-
ed, the I-flag is cleared to disable any further interrupt. But
as user sets I-flag in interrupt routine, some further inter-
rupt can be serviced even if certain interrupt is in progress.
Example: During Timer1 interrupt is in progress, INT0 in-
terrupt serviced without any suspend.
Main Program
service
TIMER 1
service
TIMER1: PUSH
A
PUSH
PUSH
LDM
LDM
EI
X
INT0
service
Y
IENH,#80H
IENL,#0
;Enable INT0 only
;Disable other
;Enable Interrupt
enable INT0
disable other
EI
:
:
:
Occur
Occur
INT0
TIMER1 interrupt
:
:
:
enable INT0
enable other
LDM
LDM
POP
POP
POP
RETI
IENH,#0F0H ;Enable all interrupts
IENL,#0F0H
Y
X
A
In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable "EI" in the TIMER1 routine.
Figure 16-6 Execution of Multi Interrupt
MAR. 2000 Ver 1.00
75
HYNIX [ HYNIX SEMICONDUCTOR ]
