GMS81C2012/GMS81C2020
HYUNDAI MicroElectronics
.
Internal bus line
I-flag is in PSW, it is cleared by "DI", set by
"EI" instruction. When it goes interrupt service,
I-flag is cleared by hardware, thus any other
Interrupt Enable
Register (Higher byte)
[0E2H]
IENH
IRQH
[0E4H]
interrupt are inhibited. When interrupt service is
completed by "RETI" instruction, I-flag is set to
"1" by hardware.
INT0IF
INT0
INT1IF
T0IF
INT1
Timer 0
Timer 1
Release STOP
T1IF
To CPU
I-flag
Interrupt Master
Enable Flag
IRQL
[0E5H]
A/D Converter
Watchdog Timer
BIT
ADIF
WDTIF
BITIF
Interrupt
Vector
Address
Generator
Serial
SIOIF
Communication
Interrupt Enable
Register (Lower byte)
[0E3H]
IENL
Internal bus line
Figure 16-2 Block Diagram of Interrupt
-
-
-
-
-
-
R/W R/W
R/W R/W
T0E
-
-
ADDRESS: 0E2H
INITIAL VALUE: 0000 ----B
INT0E INT1E
T1E
IENH
MSB
LSB
Timer/Counter 1 interrupt enable flag
Timer/Counter 0 interrupt enable flag
External interrupt 1 enable flag
External interrupt 0 enable flag
VALUE
0: Disable
1: Enable
-
-
-
-
-
-
R/W R/W R/W R/W
ADE WDTE BITE SPIE
MSB
-
-
ADDRESS: 0E3H
INITIAL VALUE: 0000 ----B
IENL
LSB
Serial Communication interrupt enable flag
Basic Interval imer interrupt enable flag
Watchdog timer interrupt enable flag
A/D Convert interrupt enable flag
Figure 16-3 Interrupt Enable Flag
72
MAR. 2000 Ver 1.00
HYNIX [ HYNIX SEMICONDUCTOR ]
