HYUNDAI MicroElectronics
GMS81C2012/GMS81C2020
14.1 Transmission/Receiving Timing
The serial transmission is started by setting SIOST(bit1 of
SIOM) to “1”. After one cycle of SCK, SIOST is cleared
automatically to “0”. The serial output data from 8-bit shift
register is output at falling edge of SCLK. And input data
is latched at rising edge of SCLK pin. When transmission
clock is counted 8 times, serial I/O counter is cleared as
‘0”. Transmission clock is halted in “H” state and serial I/
O interrupt(IFSIO) occurred.
SIOST
SCLK [R53]
(POL=0)
D0
D1
D2
D3
D4
D5
D6
D7
SOUT [R55]
D0
D1
D2
D3
D4
D5
D6
D7
SIN [R54]
(IOSW=0)
IOSWIN [R55]
(IOSW=1)
D0
D1
D2
D3
D4
D5
D6
D7
SIOSF
(SPI Status)
SPIIF
(SPI Int. Req)
Figure 14-3 SPI Timing Diagram at POL=0
SIOST
SCLK [R53]
(POL=1)
D0
D1
D2
D3
D4
D5
D6
D7
SOUT [R55]
SIN [R54]
(IOSW=0)
D0
D1
D2
D3
D4
D5
D6
D6
D7
D7
IOSWIN [R55]
(IOSW=1)
D0
D1
D2
D3
D4
D5
SIOSF
(SPI Status)
SPIIF
(SPI Int. Req)
Figure 14-4 SPI Timing Diagram at POL=1
MAR. 2000 Ver 1.00
67
HYNIX [ HYNIX SEMICONDUCTOR ]
