GMS81C2012/GMS81C2020
HYUNDAI MicroElectronics
If it needed more higher frequency of PWM, it should be
reduced resolution.
The bit POL of TM1 decides the polarity of duty cycle.
If the duty value is set same to the period value, the PWM
output is determined by the bit POL (1: High, 0: Low). And
if the duty value is set to "00H", the PWM output is deter-
mined by the bit POL (1: Low, 0: High).
Frequency
Resolution
T1CK[1:0]
T1CK[1:0]
T1CK[1:0]
= 10(2uS)
= 00(250nS) = 01(500nS)
It can be changed duty value when the PWM output. How-
ever the changed duty value is output after the current pe-
riod is over. And it can be maintained the duty value at
present output when changed only period value shown as
Figure 12-14. As it were, the absolute duty time is not
changed in varying frequency. But the changed period val-
ue must greater than the duty value.
10-bit
9-bit
8-bit
7-bit
3.9KHz
7.8KHz
0.98KHZ
1.95KHz
3.90KHz
7.81KHz
0.49KHZ
0.97KHz
1.95KHz
3.90KHz
15.6KHz
31.2KHz
Table 12-2 PWM Frequency vs. Resolution at 4MHz
ADDRESS : D2H
RESET VALUE : 00000000
T1CK1
X
T1CK0
X
T1CN
X
T1ST
X
POL
16BIT
PWM1E
CAP1
TM1
X
-
0
-
1
-
0
-
ADDRESS : D5H
RESET VALUE : ----0000
PWM1HR3PWM1HR2PWM1HR1PWM1HR0
PWM1HR
Bit Manipulation Not Available
-
-
-
-
X
X
X
X
Period High
PWM1HR[3:2]
Duty High
X : The value "0" or "1" corresponding your operation.
T1ST
T1PPR(8-bit)
COMPARATOR
T0 clock source
[T0CK]
0 : Stop
1 : Clear and Start
R56/
PWM1O/T1O
S
R
Q
CLEAR
1
MUX
(2-bit)
T1 ( 8-bit )
PWM1O
[R5FUNC.6]
1
2
8
÷
÷
÷
POL
fXI
COMPARATOR
T1CN
Slave
T1CK[1:0]
T1PDR(8-bit)
PWM1HR[1:0]
Master
T1PDR(8-bit)
Figure 12-12 PWM Mode
60
MAR. 2000 Ver 1.00
HYNIX [ HYNIX SEMICONDUCTOR ]
