GMS81C2012/GMS81C2020
HYUNDAI MicroElectronics
12.2 16-bit Timer / Counter Mode
The Timer register is being run with 16 bits. A 16-bit timer/
counter register T0, T1 are increased from 0000H until it
matches TDR0, TDR1 and then resets to 0000H. The
match output generates Timer 0 interrupt not Timer 1 in-
terrupt.
The clock source of the Timer 0 is selected either internal
or external clock by bit T0CK[2:0].
In 16-bit mode, the bits T1CK[1:0] and 16BIT of TM1
should be set to "1" respectively.
7
-
6
-
5
4
3
2
1
0
ADDRESS: 0D0H
INITIAL VALUE: --000000B
TM0
TM1
CAP0 T0CK2 BT0TCKL1T0CK0 T0CN T0ST
0
X
-
-
X
X
X
X
X means don’t care
7
6
5
4
3
2
1
0
ADDRESS: 0D2H
INITIAL VALUE: 00H
POL 16BIT PWM1E CAP1 BT1TCKL1T1CK0 T1CN T1ST
0
0
X
1
1
1
X
X
X means don’t care
T0CK[2:0]
EDGE
DETECTOR
EC0 PIN
XIN PIN
111
000
T0ST
2
÷ꢀ
0: Stop
1: Clear and start
4
÷ꢀ
÷ꢀ
001
010
011
0
8
T1 + T0
(16-bit)
1
clear
÷ꢀꢁꢂ
÷ꢀꢃꢂꢄ
100
101
TIMER 0
INTERRUPT
(Not Timer 1 interrupt)
T0CN
512
÷ꢀ
T0IF
F/F
2048
÷ꢀ
Comparator
110
MUX
TDR1 + TDR0
(16-bit)
T0O PIN
Lower byte
Higher byte
COMPARE DATA
TIMER 0 + TIMER 1
TIMER 0 (16-bit)
→
Figure 12-7 16-bit Timer/Counter
54
MAR. 2000 Ver 1.00
HYNIX [ HYNIX SEMICONDUCTOR ]
