GMS81C2012/GMS81C2020
HYUNDAI MicroElectronics
Bit 7
Basic Interval Timer Data Register
WAKEUP RCWDT
Address
Name
BITR1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ECH
CKCTLR1
WDTR
ECH
EDH
EFH
F4H
F5H
-
WDTON
BTCL
BTS2
BTS1
BTS0
WDTCL 7-bit Watchdog Counter Register
PFDR2
-
-
-
-
-
-
-
-
-
-
-
-
-
BUZO
-
PFDIS
EC0
-
PFDM
INT1
-
PFDS
INT0
T0O
R0FUNC
R4FUNC
PWM1O/
T1O
F6H
R5FUNC
-
-
-
-
-
-
-
F7H
F8H
F9H
FAH
FBH
R6FUNC
R7FUNC
R5NODR
SCMR
AN7
AN6
AN5
AN4
AN3
AN11
NODR3
CS0
AN2
AN10
NODR2
SUBOFF
-
AN1
AN9
AN0
AN8
-
-
-
-
NODR4
CS1
-
NODR7
NODR6
NODR5
NODR1
NODR0
-
-
-
-
-
-
CLKSEL MAINOFF
RA0
RA
-
-
Table 8-3 Control Registers of GMS81C2020
These registers of shaded area can not be access by bit manipulation instruction as " SET1, CLR1 ", but should be access by reg-
ister operation instruction as " LDM dp,#imm ".
1.The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR.
2.The register PFDR only be implemented on devices, not on In-circuit Emulator.
34
MAR. 2000 Ver 1.00
HYNIX [ HYNIX SEMICONDUCTOR ]
