HYUNDAI MicroElectronics
GMS81C2012/GMS81C2020
Bit 7
Address
C0H
C1H
C2H
C3H
C4H
C5H
C6H
C7H
C8H
C9H
CAH
CBH
CCH
CDH
CEH
CFH
D0H
Name
R0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R0 Port Data Register (Bit[7:0])
R0 Port Direction Register (Bit[7:0])
R1 Port Data Register (Bit[7:0])
R1 Port Direction Register (Bit[7:0])
R2 Port Data Register (Bit[7:0])
R2 Port Direction Register (Bit[7:0])
R3 Port Data Register (Bit[5:0])
R3 Port Direction Register (Bit[5:0])
R4 Port Data Register (Bit[3:0])
R4 Port Direction Register (Bit[3:0])
R5 Port Data Register (Bit[7:0])
R5 Port Direction Register (Bit[7:0])
R6 Port Data Register (Bit[7:0])
R6 Port Direction Register (Bit[7:0])
R7 Port Data Register (Bit[5:0])
R7 Port Direction Register (Bit[5:0])
R0IO
R1
R1IO
R2
R2IO
R3
R3IO
R4
R4IO
R5
R5IO
R6
R6IO
R7
R7IO
TM0
-
-
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T1CN
T0ST
T1ST
T0/TDR0/
CDR0
D1H
D2H
D3H
Timer0 Register / Timer0 Data Register / Capture0 Data Register
TM1
POL
Timer1 Data Register / PWM1 Period Register
Timer1 Register / Capture1 Data Register / PWM1 Duty Register
16BIT
PWM1E
CAP1
T1CK1
T1CK0
TDR1/
T1PPR
T1/CDR1/
T1PDR
D4H
D5H
DEH
E0H
E1H
E2H
E3H
E4H
E5H
E6H
EAH
EBH
PWM1HR PWM1 High Register(Bit[3:0])
BUR
BUCK1
POL
BUCK0
IOSW
BUR5
SM1
BUR4
SM0
BUR3
SCK1
BUR2
SCK0
BUR1
BUR0
SIOM
SIOR
IENH
IENL
SIOST
SIOSF
SPI DATA REGISTER
INT0E
ADE
INT1E
WDTE
INT1IF
WDTIF
T0E
BITE
T0IF
BITIF
T1E
SPIE
T1IF
SPIIF
-
-
-
-
IRQH
IRQL
IEDS
ADCM
ADCR
INT0IF
ADIF
-
-
-
-
IED1H
ADS1
IED1L
ADS0
IED0H
ADST
IED0L
ADSF
-
ADEN
ADS3
ADS2
ADC Result Data Register
Table 8-3 Control Registers of GMS81C2020
These registers of shaded area can not be access by bit manipulation instruction as " SET1, CLR1 ", but should be access by reg-
ister operation instruction as " LDM dp,#imm ".
MAR. 2000 Ver 1.00
33
HYNIX [ HYNIX SEMICONDUCTOR ]
