GMS82512/16/24
HYUNDAI MicroElectronics
OP
CODE
BYTE CYCLE
FLAG
NVGBHIZC
NO.
MNENONIC
OPERATION
NO.
2
2
2
3
3
2
2
1
3
3
1
2
2
3
1
1
2
3
3
2
2
2
2
3
3
2
2
1
1
3
3
3
2
2
2
3
2
2
2
3
2
1
2
2
3
1
1
3
NO
2
3
4
4
5
6
6
3
5
5
2
4
5
5
2
2
6
3
5
4
2
3
4
4
5
6
6
3
4
4
4
5
2
3
4
4
2
3
4
4
5
2
4
5
5
9
2
5
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
EOR #imm
EOR dp
A4
A5
A6
A7
B5
96
Exclusive OR
A ꢀ A (M)
EOR dp + X
EOR !abs
EOR !abs + Y
EOR [ dp + X]
EOR [dp] + Y
EOR {X}
N - - - - - Z -
97
94
EOR1 M.bit
EOR1B M.bit
INC A
AB
AB
88
- - - - - - - C
- - - - - - - C
N - - - - - ZC
Bit exclusive-OR C-flag : C ꢀ C (M.bit)
Bit exclusive-OR C-flag and NOT : C ꢀ C (M.bit)
Increment
INC dp
89
(M) ꢀ (M) + 1
INC dp + X
INC !abs
INC X
99
98
N - - - - - Z -
8F
9E
9D
1B
1F
3F
C4
C5
C6
C7
D5
D6
D7
D4
DB
CB
CB
E4
1E
CC
CD
DC
3E
C9
D9
D8
7D
48
INC Y
INCW dp
JMP !abs
JMP [!abs]
JMP [dp]
N - - - - - Z -
- - - - - - - -
Increment memory pair : (dp+1)(dp) ꢀ {(dp+1)(dp)} + 1
Unconditional jump
PC ꢀ jump address
LDA #imm
Load accumulator
100 LDA dp
A ꢀ (M)
101 LDA dp + X
102 LDA !abs
103 LDA !abs + Y
104 LDA [dp + X]
105 LDA [dp]+Y
106 LDA {X}
107 LDA {X}+
108 LDC M.bit
109 LDCB M.bit
110 LDM dp,#imm
111 LDX #imm
112 LDX dp
N - - - - - Z -
X-register auto-increment : A ꢀ (M), X ꢀ X + 1
Load C-flag : C ꢀ (M.bit)
- - - - - - - C
- - - - - - - C
- - - - - - - -
Load C-flag with NOT : C ꢀ (M.bit)
Load memory with immediate data : (M) ꢀ imm
Load X-register
X ꢀ (M)
N - - - - - Z -
113 LDX dp + Y
114 LDX !abs
115 LDY #imm
116 LDY dp
Load X-register
Y ꢀ (M)
N - - - - - Z -
N - - - - - Z -
N - - - - - ZC
117 LDY dp + Y
118 LDY !abs
119 LDYA dp
120 LSR A
Load YA : YA ꢀ (dp+1)(dp)
Logical shift right
121 LSR dp
49
59
58
7 6 5 4 3 2 1 0ꢁꢁ C
"0"ꢆꢁꢆꢁ ꢁ ꢁ ꢁ ꢁ ꢁ ꢁ ꢁ ꢁ
122 LSR dp + X
123 LSR !abs
124 MUL
5B
FF
4B
N - - - - - Z -
- - - - - - - -
- - - - - - - -
Multiply : YA ꢀ Y x A
No operation
125 NOP
126 NOT1 M.bit
Bit complement : (M.bit) ꢀ (M.bit)
xi
FEB. 2000 Ver 1.00
HYNIX [ HYNIX SEMICONDUCTOR ]
