HYUNDAI MicroElectronics
GMS82512/16/24
19. POWER FAIL PROCESSOR
The GMS825xx has an on-chip power fail detection cir-
cuitry to immunize against power noise. A configuration
register, PFDR, can enable or disable the power fail detect
circuitry. Whenever VDD falls close to or below power fail
voltage for 100ns, the power fail situation may reset or
freeze MCU according to PFR bit of PFDR. Refer to “7.4
DC Electrical Characteristics” on page 11.
Note: If power fail voltage is selected to 3.0V on 3V oper-
.
ation, MCU is freezed at all the times
Power FailFunction
Enable/Disable
OTP
by PFD flag
MASK
by PFD flag
Level Selection
by PFV flag by mask option
In the in-circuit emulator, power fail function is not imple-
mented and user can not experiment with it. Therefore, af-
ter final development of user program, this function may
be experimented or evaluated.
Table 19-1 Power fail processor
Note: User can select power fail voltage level according to
PFV bit of PFDR at the OTP(GMS82524T) but must select
the power fail voltage level to define PFD option of “Mask
Order & Verification Sheet” at the mask chip(GMS825xx).
Because the power fail voltage level of mask chip
(GMS825xx) is determined according to mask option re-
gardless of PFV bit of PFDR
R/W R/W R/W R/W
7
6
5
4
3
2
1
0
ADDRESS: 0F9
INITIAL VALUE: ---- 1100
H
PFV
PFD
PFR PFS
PFDR
B
Power Fail Status
0: Normal operate
1: Set to “1” if power fail is detected
Operation Mode
0: Normal operation regardless of power fail
1: MCU will be reset by power fail detection
Disable Flag
0: Power fail detection enable
1: Power fail detection disable
Power Fail Voltage Selection Flag
0: 2.4V
1: 3.0V
Figure 19-1 Power Fail Voltage Detector Register
FEB. 2000 Ver 1.00
61
HYNIX [ HYNIX SEMICONDUCTOR ]
