GMS81C1102/GMS81C1202
6. CONTROL OPERATION & etc.
OP BYTE CYCLE
FLAG
NO.
1
MNEMONIC
OPERATION
Software interrupt : B ← ”1”, M(sp) ← (pc ), sp ←sp-1,
NVGBHIZC
CODE NO
NO
H
0F
1
8
---1-0--
M(s) ← (pc ), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1,
L
BRK
pc ← ( 0FFDE ) , pc ← ( 0FFDF ) .
L
H
H
H
2
3
60
E0
FF
0D
2D
4D
6D
0E
2E
4E
6E
1
1
1
1
1
1
1
1
1
1
1
3
3
2
4
4
4
4
4
4
4
4
-----0--
-----1--
--------
DI
Disable interrupts : I ← “0”
EI
Enable interrupts : I
No operation
←
“1”
4
NOP
5
POP A
POP X
POP Y
POP PSW
PUSH A
PUSH X
PUSH Y
PUSH PSW
sp
sp
sp
sp
sp + 1, A
sp + 1, X
sp + 1, Y
M( sp )
M( sp )
M( sp )
←
←
←
←
←
←
←
6
--------
restored
--------
7
8
sp + 1, PSW
←
M( sp )
9
M( sp ) ← A , sp ← sp - 1
10
11
12
M( sp )
M( sp )
←
←
X , sp
Y , sp
←
←
sp - 1
sp - 1
M( sp ) ← PSW , sp ← sp - 1
Return from subroutine
13
6F
1
5
--------
RET
sp ← sp +1, pc ← M( sp ), sp ← sp +1, pc ← M( sp )
L
H
Return from interrupt
14
15
7F
EF
1
1
6
3
sp ← sp +1, PSW ← M( sp ), sp ← sp + 1,
restored
--------
RETI
pc ← M( sp ), sp ← sp + 1, pc ← M( sp )
L
H
STOP
Stop mode ( halt CPU, stop oscillator )
Jan. 2002 Ver 2.0
vii
HYNIX [ HYNIX SEMICONDUCTOR ]
