GM82C765B
SYMBOL
t
t
t
t
t
t
t
t
t
t
t
PARAMETER
IDX
DIRC
RD
WR
RD
MIN
2
MAX
UNITS
MCY
MCY
nS
nS
IDX
STD
MR
MW
MRW
CA
CAS
XCA
XTS
TCR
TCW
Index Pulse Width
Hold Time after
STEP
96
0
0
48
32
40
500
1000
0
0
192
384
uS
Delay from DMA
Delay from DMA
or
WR
Response from DMA High
MCY
MCY
MCY
Chip Access Delay from RST Low-TTL
Chip Access Delay from
t
SRST
Low
Chip Access Delay from RST-OSC XT1 at 16MHz
XT2 Access Delay after RST 9.6MHz
TC Delay from Last DMA or IRQ,
TC Delay from Last DMA or IRQ,
RD
WR
uS
MCY
MCY
Note: CY specifies CLK1 or XT1 period
MCY specifies MCLK period, dependent on selected data rate
WCY specifies WCLK period, dependent on selected data rate
2.4 AC Timing Diagrams
(1) READ Timing
CS, DACK.
A0
,
t
AR
t
t
RA
RR
RD
t
RD
Data Valid
t
DF
DATA
t
RI
IRQ
8
HYNIX [ HYNIX SEMICONDUCTOR ]
