GM82C765B
3. ARCHITECTURE
HOST INTERFACE
The GM82C765B Floppy Disk Subsystem
Controller is a CMOS LSI device that provides
all the needed functionality between the host
u-processor peripheral Bus and the cable
Connec-tor to the Floppy Disk Drive. This CHIP
in-tegrates; Formatter/Controller Data Separation,
Write Precompensation, Data rate Seletion,
Clock generation, Drive interface drivers and
receivers.
The host interface is the host microprocessor
peripheral bus. This bus is composed of eight
control signals and eight data signals. In the
special or PC AT modes, IRQ and DMA request
are tri-stated and qualified enable, internally
provided by the operations register. The data bus,
DMA, and IRQ outputs are designed to handle 20
LS-TTL loading.
8 Bit
DATA
DATA
MASTER
STATUS REG
CONTROL
REGISTER
OPERATION
BUS
REGISTER
REGISTER
8 Bit INTERNAL DATA BUS
DRV
MCLK
HS
CLOCK
AND
RAM
DISK
24 ´
8
01
ALU
RD
INTERFACE
CONTROL
REGISTER
TIMING
STEP
DIRC
RWC
WR
ROM
02
INSTRUCTION
DECODE
GENERATOR
CS
A0
1KÏ16
WCLK
DS1 -
4
HOST
DACK
TC
SCLK
TROO
INTERFACE
DMA
IRQ
WP
PROGRAM
COUNTER
SATE
LDCR
LDOR
MS
TIMER
DCHG *
MACHINE
FLAG
LOGIC
WE
CLK1
CLK2
CRYSTAL
WD
DATA ENCODER
DECODER
CRC GENERATOR
WRITE
DIGITAL DATA
SEPARATOR
OSc´ 2
PCVAL
PRECOMPENSATION
PLCC version of GM82C765B only
Fig 1. GM82C765B Internal Block Diagram
11
HYNIX [ HYNIX SEMICONDUCTOR ]
