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GM76V256CLLET-10 参数 Datasheet PDF下载

GM76V256CLLET-10图片预览
型号: GM76V256CLLET-10
PDF下载: 下载PDF文件 查看货源
内容描述: [Standard SRAM, 32KX8, 100ns, CMOS, PDSO28, 8 X 13.40 MM, TSOP1-28]
分类和应用: 静态存储器光电二极管内存集成电路
文件页数/大小: 10 页 / 136 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
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GM76V256C Series  
TIMING DIAGRAM  
READ CYCLE 1  
tRC  
ADDR  
OE  
tAA  
tOE  
tOH  
tOLZ  
CS  
tACS  
tCLZ  
tOHZ  
tCHZ  
High-Z  
Data  
Out  
Data Valid  
Note(READ CYCLE):  
1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and arenot  
referenced to output voltage levels.  
2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given device  
and from device to device.  
3. /WE is high for the read cycle.  
READ CYCLE 2  
tRC  
ADDR  
tAA  
tOH  
tOH  
Data  
Out  
Previous Data  
Data Valid  
Note(READ CYCLE):  
1. /WE is high for the read cycle.  
2. Device is continuously selected /CS= VIL.  
3. /OE =VIL.  
Rev 00 / Jul. 2000  
5