GM76U8128CL/CLL
Data Retention Characteristics
Symbol
Parameter
Min Typ Max Unit
2.0
-
3.3
V
VCCR
Data Retention Supply Voltage
L - Version
LL - Version
-
-
1
0.5
50
15*
GM76U8128C
Data Retention
ICCR
Current
VCC=3.0V
uA
L - Version
LL - Version
GM76U8128C-E
-
-
1
0.5
30
20*
GM76U8128C-I
Chip Select to Data Retention Time
Operation Recovery Time
0
-
-
-
-
ns
ns
tCDR
tR
tRC**
* 3uA max at T
A
= 0 ~ 40C
** tRC = Read Cycle
* Low VCC Data Retention Mode: (1) /CS1 Controlled
Data Retention Mode
t
CDR
t
R
VCC
2.7V
2.2V
VCCR1
/CS1>=VCCR - 0.2V
/CS1
0V
* Low VCC Data Retention Mode: (2) CS2 Controlled
Data Retention Mode
t
CDR
t
R
VCC
2.7V
CS2
VCCR2
0.4V
0V
CS2 <= 0.2V
Notes: In Data Retention Mode, CS2 controls the Address, /WE, /CS1, /OE and DIN buffer. If CS2 controls
data retention mode, VIN for these inputs can be in the high impedance state. If /CS1 controls the
_
>
data retention mode, CS2 must satisfy either CS2 VCCR - 0.2V or CS2<=0.2V. The other input levels
(Address, /WE, /OE, I/O) can be in the high impedance state.
117
HYNIX [ HYNIX SEMICONDUCTOR ]
