GM76U8128CL/CLL
Write Cycle (3) (CS2 Controlled) (Notes 4)
t
WC
ADD
t
AS
t
WR
t
WP
/WE
t
t
CW2
CS2
CW1
/CS1
t
WHZ
t
CLZ
DOUT
t
DW
t
DH
DIN
VALID DATA
Notes:
1. /WE is High for Read Cycle.
2. Assuming that /CS1 Low transition or CS2 High transition occurs coincident with or after /WE Low
transition. Outputs remain in a high impedance state.
3. Assuming that /CS1 High transition or CS2 Low transition occurs coincident with or prior to /WE High
transition. Outputs remain in a high impedance state.
4. Assuming that /OE is high for write cycle. Outputs are in a high impedance state during this period.
116
HYNIX [ HYNIX SEMICONDUCTOR ]
