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GM76C256CLLEFW 参数 Datasheet PDF下载

GM76C256CLLEFW图片预览
型号: GM76C256CLLEFW
PDF下载: 下载PDF文件 查看货源
内容描述: 32K ×8位的5.0V低功耗CMOS SRAM慢 [32K x8 bit 5.0V Low Power CMOS slow SRAM]
分类和应用: 静态存储器
文件页数/大小: 11 页 / 177 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
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GM76C256C Series  
DC CHARACTERISTICS  
Vcc = 5V ±10%, TA = 0°C to 70°C (Normal)/-25°C to 85°C (Extended), unless otherwise specified.  
Symbol  
ILI  
ILO  
Parameter  
Input Leakage Current  
Output Leakage Current  
Test Condition  
Vss < VIN < Vcc  
Min. Typ. Max. Unit  
-1  
-1  
-
-
1
1
uA  
uA  
Vss < VOUT < Vcc, /CS = VIH or  
/OE = VIH or /WE = VIL  
/CS = VIL, VIN = VIH or VIL,  
VIN = VIH or VIL, II/O = 0mA  
/CS = VIL, VIN = VIH or VIL,  
Min. Duty Cycle = 100%, II/O = 0mA  
/CS= VIH  
Icc  
Operating Power Supply  
Current  
Average Operating Current  
-
-
-
-
-
-
10  
70  
1
mA  
mA  
mA  
ICC1  
ISB  
TTL Standby Current  
(TTL Inputs)  
VIN = VIH or VIL  
ISB1  
CMOS Standby Current  
(CMOS Inputs)  
/CS > Vcc - 0.2V,  
VIN > Vcc - 0.2V or  
VIN < Vss + 0.2V  
L
-
-
-
-
-
-
-
-
-
-
-
40  
20  
60  
30  
0.4  
-
uA  
uA  
uA  
uA  
V
LL  
LE  
LLE  
VOL  
VOH  
Output Low Voltage  
Output High Voltage  
IOL = 2.1mA  
IOH = -1.0mA  
2.4  
V
Note : Typical values are at Vcc =5.0V, TA = 25°C  
AC CHARACTERISTICS(I)  
Vcc = 5V ±10%, TA = 0°C to 70°C (Normal) / -25°C to 85°C (Extended) unless otherwise specified.  
-55  
Max. Min.  
-70  
Max. Min  
-85  
Max.  
#
Symbol  
Parameter  
Unit  
Min.  
READ CYCLE  
1
2
3
4
5
6
7
8
9
tRC  
tAA  
tACS  
tOE  
tCLZ  
tOLZ  
tCHZ  
tOHZ  
tOH  
Read Cycle Time  
Address Access Time  
Chip Select Access Time  
Output Enable to Output Valid  
Chip Select to Output in Low Z  
Output Enable to Output in Low Z  
Chip Disable to Output in High Z  
Out Disable to Output in High Z  
Output Hold from Address Change  
55  
-
-
-
70  
-
-
-
85  
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
55  
55  
30  
-
70  
70  
35  
-
85  
85  
45  
-
-
-
-
10  
5
0
0
5
10  
5
0
0
5
10  
5
0
0
5
-
-
-
20  
20  
-
30  
30  
-
30  
30  
-
WRITE CYCLE  
10 tWC  
11 tCW  
12 tAW  
13 tAS  
14 tWP  
15 tWR  
16 tWHZ  
17 tDW  
18 tDH  
19 tOW  
Write Cycle Time  
55  
50  
50  
0
40  
0
0
25  
0
-
-
-
-
-
-
20  
-
-
-
70  
65  
65  
0
50  
0
0
30  
0
-
-
-
-
-
-
25  
-
-
-
85  
75  
75  
0
60  
0
0
40  
0
-
-
-
-
-
-
30  
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Selection to End of Write  
Address Valid to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
Write to Output in High Z  
Data to Write Time Overlap  
Data Hold from Write Time  
Output Active from End of Write  
5
5
5
Rev 03 / Apr. 2000  
3
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