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GM71V17403CT-7 参数 Datasheet PDF下载

GM71V17403CT-7图片预览
型号: GM71V17403CT-7
PDF下载: 下载PDF文件 查看货源
内容描述: X4 EDO页模式DRAM\n [x4 EDO Page Mode DRAM ]
分类和应用: 内存集成电路光电二极管动态存储器
文件页数/大小: 10 页 / 101 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
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GM71V17403C  
GM71VS17403CL  
Self Refresh Mode ( L-version )  
GM71VS17403  
CL-5  
GM71VS17403 GM71VS17403  
CL-6 CL-7  
Unit  
Note  
Symbol  
Parameter  
Min Max Min Max Min Max  
RAS Pulse Width ( Self-refresh )  
100  
-
100  
-
100  
-
ms  
t
RASS  
RPS  
CHS  
RAS Precharge Time ( Self-refresh )  
CAS Hold Time ( Self-refresh )  
90  
-
-
110  
-50  
-
-
130  
-50  
-
-
ns  
ns  
t
-50  
t
Notes:  
AC Measurements assume tT = 2ns.  
1.  
2.  
An initial pause of 200us is required after power up followed by a minimum of eight  
initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-  
RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS  
refresh cycles are required.  
Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a  
reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is  
controlled exclusively by tCAC.  
3.  
4.  
Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a  
reference point only; if tRAD is greater than the specified tRAD(max) limit, then access time is  
controlled exclusively by tAA.  
5. Either tODD or tCDD must be satisfied.  
6. Either tDZO or tDZC must be satisfied.  
VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also,  
transition times are measured between VIH(min) and VIL(max).  
7.  
8.  
9.  
Assume that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum  
recommended value shown in this table, tRAC exceeds the value shown.  
Measured with a load circuit equivalent to 1 TTL loads and 100pF.  
10. Assume that tRCD >=tRCD(max) and tRCD +  
t
CAC(max) >= tRAD + AA(max).  
t
Assume that tRAD >=tRAD(max) and tRCD +  
t
CAC(max) <= tRAD + tAA(max).  
11.  
12.  
13.  
Either tRCH or tRRH must be satisfied for a read cycles.  
tOFF(max) and tOEZ(max) define the time at which the outputs achieve the open circuit condition  
and are not referenced to output voltage levels.  
Rev 0.1 / Apr’01