欢迎访问ic37.com |
会员登录 免费注册
发布采购

H6850 参数 Datasheet PDF下载

H6850图片预览
型号: H6850
PDF下载: 下载PDF文件 查看货源
内容描述: 新型低成本绿色节能PWM控制器 [Novel Low Cost Green-Power PWM Controller]
分类和应用: 控制器
文件页数/大小: 13 页 / 419 K
品牌: HSMC [ HI-SINCERITY MOCROELECTRONICS ]
 浏览型号H6850的Datasheet PDF文件第4页浏览型号H6850的Datasheet PDF文件第5页浏览型号H6850的Datasheet PDF文件第6页浏览型号H6850的Datasheet PDF文件第7页浏览型号H6850的Datasheet PDF文件第9页浏览型号H6850的Datasheet PDF文件第10页浏览型号H6850的Datasheet PDF文件第11页浏览型号H6850的Datasheet PDF文件第12页  
Spec. No. : IC200804  
Issued Date : 2008.09.19  
Revised Date :  
HI-SINCERITY  
MICROELECTRONICS CORP.  
Page No. : 8/13  
starts, the delay time is set. When the RI  
Over Voltage Protection (OVP)  
resistance is 100Kohm, the delay time  
TOLP&SCP is between 33mS and 50mS. The  
relationship between RI and TOLP&SCP  
follows the below equation.  
There is a 34V over-voltage protection  
circuit in the H6850 to improve the credibility  
and extend the life of the chip. When the  
VDD voltage is over 34V, the GATE pin is to  
shutdown immediately and the VDD voltage  
is to descend rapidly.  
RI × 2  
RI ×3  
6×103  
(mS) < TOLP&SCP  
<
(mS)  
6×103  
Anti Intermission Surge  
GATE Driver & Soft Clamped  
When the power supplies change the  
heavy load to light load immediately, there  
could be tow phenomena caused by system  
delay. They are output voltage overshot and  
intermission surge. To avoid it, the anti  
intermission surge is built in the H6850. If it  
occurs, the FB current is to increase rapidly,  
the GATE would be cut off for a while, VDD  
pin voltage descends gradually. When VDD  
reaches 9.4V, the GATE pin would operate  
again, which the frequency is 22KHz.  
The H6850’ output designs a totem pole  
to drive a periphery power MOSFET. The  
dead time is introduced to minimize the  
transfixion current during the output  
operating. The novel soft clamp technology  
is introduced to protect the periphery power  
MOSFET from breaking down and current  
saturation of the Zener.  
Low EMI technique  
The frequency low EMI technique is  
introduced in the H6850. As following figure,  
the internal oscillation frequency is  
modulated by itself. A whole surge cycle  
includes 128 pulses and the jittering ranges  
from -4% to +4%. Thus, the function could  
minimize the electromagnetic interferer from  
the power supply module.  
Leading-edge Blanking (LEB)  
Each time the power MOSFET is  
switched on, a turn-on spike will inevitably  
occur at the Sense pin, which would disturb  
the internal signal from the sampling of the  
RSENSE. There is a 300nS leading edge  
blanking time built in to avoid the effect of  
the turn-on spike, and the power MOSFET  
cannot be switched off during the moment.  
So that the conventional external RC  
filtering on sense input is no longer required.  
Frequency(HZ)  
70K  
65K  
60K  
Time  
Frequency low EMI  
H6850  
H6850P, H6850S,H6850NF  
HSMC Product Specification  
 复制成功!