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H6850 参数 Datasheet PDF下载

H6850图片预览
型号: H6850
PDF下载: 下载PDF文件 查看货源
内容描述: 新型低成本绿色节能PWM控制器 [Novel Low Cost Green-Power PWM Controller]
分类和应用: 控制器
文件页数/大小: 13 页 / 419 K
品牌: HSMC [ HI-SINCERITY MOCROELECTRONICS ]
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HI-SINCERITY
MICROELECTRONICS CORP.
starts, the delay time is set. When the RI
resistance is 100Kohm, the delay time
T
OLP&SCP
is between 33mS and 50mS. The
relationship between RI and T
OLP&SCP
follows the below equation.
Spec. No. : IC200804
Issued Date : 2008.09.19
Revised Date :
Page No. : 8/13
Over Voltage Protection (OVP)
There is a 34V over-voltage protection
circuit in the H6850 to improve the credibility
and extend the life of the chip. When the
VDD voltage is over 34V, the GATE pin is to
shutdown immediately and the VDD voltage
is to descend rapidly.
RI
×
2
RI
×
3
(
mS
)
<
T
OLP
&
SCP
<
(
mS
)
6
×
10
3
6
×
10
3
Anti Intermission Surge
When the power supplies change the
heavy load to light load immediately, there
could be tow phenomena caused by system
delay. They are output voltage overshot and
intermission surge. To avoid it, the anti
intermission surge is built in the H6850. If it
occurs, the FB current is to increase rapidly,
the GATE would be cut off for a while, VDD
pin voltage descends gradually. When VDD
reaches 9.4V, the GATE pin would operate
again, which the frequency is 22KHz.
GATE Driver & Soft Clamped
The H6850’ output designs a totem pole
to drive a periphery power MOSFET. The
dead time is introduced to minimize the
transfixion current during the output
operating. The novel soft clamp technology
is introduced to protect the periphery power
MOSFET from breaking down and current
saturation of the Zener.
Low EMI technique
The frequency low EMI technique is
introduced in the H6850. As following figure,
the internal oscillation frequency is
modulated by itself. A whole surge cycle
includes 128 pulses and the jittering ranges
from -4% to +4%. Thus, the function could
minimize the electromagnetic interferer from
the power supply module.
Frequency(HZ)
70K
Leading-edge Blanking (LEB)
Each time the power MOSFET is
switched on, a turn-on spike will inevitably
occur at the Sense pin, which would disturb
the internal signal from the sampling of the
R
SENSE
. There is a 300nS leading edge
blanking time built in to avoid the effect of
the turn-on spike, and the power MOSFET
cannot be switched off during the moment.
So that the conventional external RC
filtering on sense input is no longer required.
65K
60K
Time
Frequency low EMI
H6850
H6850P, H6850S,H6850NF
HSMC Product Specification