Spec. No. : IC200804
Issued Date : 2008.09.19
Revised Date :
HI-SINCERITY
MICROELECTRONICS CORP.
Page No. : 7/13
To decrease the standby consumption
of the power supply, Chip-Rail introduces
the Cycle Reset Mode technology (CRM). If
the feedback current is over 0.59mA, mode
controller of the H6850 would reset internal
register all the time and cut off the GATE pin.
While the output voltage is lower than the
set value, the register would be set, the
GATE pin operate again. So the frequency
of the internal OSC is invariable, the register
would reset some pulses so that the
practical frequency is decreased at the
GATE pin.
MOSFET comes into being a voltage VSENSE
on the Sense pin cycle-by-cycle, which
compares to the internal reference voltage,
and controls the reverse of the internal
register, limits the peak current IMAX of the
primary of the transformer. The transformer
1
energy is E = × L× IMAX 2 . So adjusting
2
the RSENSE can set the maximal output
power of the power supple. The current
flowing by the power MOSFET has an extra
VIN
value ( ΔI =
×TD ) due to the system
Internal Synchronized Slop
LP
Compensation
delay time that is from detecting the current
through the Sense pin to power MOSFET off
in the H6850 (Among these, VIN is the
primary winding voltage of the transformer
and LP is the primary wind inductance). VIN
ranges from 85VAC to 264VAC. To
guarantee the output power is a constant for
universal input AC voltage, there is a
dynamic peak limit circuit to compensate the
system delay T that the system delay brings
on.
Although there are more advantages of
the current mode control than conventional
voltage mode control, there are still several
drawbacks of peak-sensing current-mode
converter, especially the open loop
instability when it operates in higher than
50% of the duty-cycle. To solve this problem,
the H6850 is introduced an internal slope
compensation adding voltage ramp to the
current sense input voltage for PWM
generation. It improves the close loop
stability greatly at CCM, prevents the
sub-harmonic oscillation and thus reduces
the output ripple voltage.
Vsense
1.10
1.05
1.00
0.95
DUTY
0.90
VSLOP = 0.33×
= 0.4389× DUTY
0.85
DUTYMAX
0.80
0.75
0.70
Duty Cycle
0.65
0% 10%20%30%40%50%60%70%80%90%
OLP&SCP
To protect the circuit from being
damaged under the over load or short circuit
condition, a smart OLP&SCP function is
implemented in the H6850. When short
circuit or over load occurs in the output end,
the feedback cycle would enhance the
voltage of FB pin, while the voltage is over
3.7V or the current from FB is below 170uA,
the internal detective circuit would send a
signal to shut down the GATE and pull down
the VDD voltage, then the circuit is restart.
To avoid the wrong operation when circuit
Slop Compensation
Current Sensing & Dynamic peak
limiting
The current flowing by the power
H6850P, H6850S,H6850NF
HSMC Product Specification
HSMC [ HI-SINCERITY MOCROELECTRONICS ]
