11
Notes:
6. This supply is optional. Required only
when negative gate drive is
implemented.
7. Maximum pulse width = 50 µs,
maximum duty cycle = 0.5%.
8. See the Slow IGBT Gate Discharge
During Fault Condition section in the
applications notes at the end of this
data sheet for further details.
21. This is the amount of time the DESAT
threshold must be exceeded before
1. In accordance with UL1577, each
optocoupler is proof tested by
applying an insulation test voltage
≥ 4500 Vrms for 1 second (leakage
V
OUT
begins to go low, and the
FAULT output to go low.
22. This is the amount of time from when
RESET is asserted low, until FAULT
output goes high. The minimum
specification of 3 µs is the guaranteed
minimum FAULT signal pulse width
when the HCPL-316J is configured
for Auto-Reset. See the Auto-Reset
section in the applications notes at
the end of this data sheet for further
details.
detection current limit, I ≤ 5 µA).
I-O
This test is performed before the
100% production test for partial
discharge (method b) shown in IEC/
EN/DIN EN 60747-5-2 Insulation
Characteristic Table, if applicable.
2. The Input-Output Momentary With-
stand Voltage is a dielectric voltage
rating that should not be interpreted
as an input-output continuous voltage
rating. For the continuous voltage
rating refer to your equipment level
safety specification or IEC/EN/DIN
EN 60747-5-2 Insulation
9. 15 V is the recommended minimum
operating positive supply voltage
(V
- V ) to ensure adequate
E
CC2
margin in excess of the maximum
threshold of 13.5 V. For High
V
UVLO+
Level Output Voltage testing, V
is
23. Common mode transient immunity in
the high state is the maximum
OH
measured with a dc load current.
When driving capacitive loads, V
tolerable dV /dt of the common
OH
CM
will approach V as I approaches
mode pulse, V , to assure that the
CC
OH
CM
zero units.
output will remain in the high state
Characteristics Table.
10. Maximum pulse width = 1.0 ms,
maximum duty cycle = 20%.
(i.e., V > 15 V or FAULT > 2 V). A
O
3. Device considered a two terminal
device: pins 1 - 8 shorted together
and pins 9 - 16 shorted together.
4. In order to achieve the absolute
maximum power dissipation
100 pF and a 3K Ω pull-up resistor is
needed in fault detection mode.
24. Common mode transient immunity in
the low state is the maximum
11. Once V
of the HCPL-316J is
OUT
allowed to go high (V
- V >
CC2
E
V
), the DESAT detection feature
UVLO
of the HCPL-316J will be the primary
source of IGBT protection. UVLO is
needed to ensure DESAT is
tolerable dV /dt of the common
CM
specified, pins 4, 9, and 10 require
ground plane connections and may
require airflow. See the Thermal
Model section in the application notes
at the end of this data sheet for
details on how to estimate junction
temperature and power dissipation. In
most cases the absolute maximum
output IC junction temperature is the
limiting factor. The actual power
dissipation achievable will depend on
the application environment (PCB
Layout, air flow, part placement,
etc.). See the Recommended PCB
Layout section in the application
notes for layout considerations.
Output IC power dissipation is
mode pulse, V , to assure that the
CM
output will remain in a low state (i.e.,
functional. Once V
> 11.6 V,
V < 1.0 V or FAULT < 0.8 V).
UVLO+
O
DESAT will remain functional until
< 12.4 V. Thus, the DESAT
25. Does not include LED2 current
during fault or blanking capacitor
discharge current.
V
UVLO-
detection and UVLO features of the
HCPL-316J work in conjunction to
ensure constant IGBT protection.
12. See the Blanking Time Control
section in the applications notes at
the end of this data sheet for further
details.
26. To clamp the output voltage at
V
- 3 V , a pull-down resistor
CC
BE
between the output and V is
EE
recommended to sink a static current
of 650 µA while the output is high.
See the Output Pull-Down Resistor
section in the application notes at the
end of this data sheet if an output
pull-down resistor is not used.
13. This is the “increasing” (i.e. turn-on
or “positive going” direction) of
V
CC2
- V .
E
14. This is the “decreasing” (i.e. turn-off
or “negative going” direction) of
27. The recommended output pull-down
resistor between V
and V does
OUT
EE
derated linearly at 10 mW/°C above
90°C. Input IC power dissipation does
not require derating.
V
- V .
not contribute any output current
when V = V
CC2 E
15. This load condition approximates the
gate load of a 1200 V/75A IGBT.
16. Pulse Width Distortion (PWD) is
.
EE
OUT
28. In most applications V
will be
CC1
5. Maximum pulse width = 10 µs,
maximum duty cycle = 0.2%. This
value is intended to allow for compo-
nent tolerances for designs with I
peak minimum = 2.0 A. See
Applications section for additional
details on I
from 3.0 A at +25°C to 2.5 A at
+100°C. This compensates for
increased I
powered up first (before V
) and
CC2
defined as |t
unit.
- t
PLH
| for any given
powered down last (after V
). This
PHL
CC2
is desirable for maintaining control of
the IGBT gate. In applications where
17. As measured from V , V to V
.
O
IN+ IN-
OUT
18. The difference between t
and t
PHL PLH
V
is powered up first, it is
CC2
between any two HCPL-316J parts
under the same test conditions.
19. Supply Voltage Dependent.
20. This is the amount of time from when
the DESAT threshold is exceeded,
until the FAULT output goes low.
important to ensure that V
remains
in+
peak. Derate linearly
low until V
reaches the proper
OH
CC1
operating voltage (minimum 4.5 V) to
avoid any momentary instability at
due to changes in
the output during V
ramp-down.
ramp-up or
OPEAK
over temperature.
CC1
V
OL
HP [ HEWLETT-PACKARD ]
