I
F
B
A
D.U.T.
+5 V
V
CC
R
L
R
M
V
O
V
FF
GND
SINGLE CHANNEL OR
COMMON V
DEVICES
CC
V
CM
+
–
PULSE GEN.
NOTE: BASE LEAD NOT CONNECTED.
Figure 10. Test Circuit for Transient Immunity and Typical Waveforms.
V
5 V
CC
Logic Family
Device No.
VCC
LSTTL
54LS14
5 V
CMOS
CD40106BM
220 Ω
5 V
15 V
R
L
D.U.T.
RL 5% Tolerance
18 kΩ* 8.2 kΩ 22 kΩ
V
CC
*The equivalent output load resistance is affected by the
LSTTL input current and is approximately 8.2 kΩ.
TTL
This is a worst case design which takes into account 25%
degradation of CTR. See App. Note 1002 to assess actual
degradation and lifetime.
LOGIC GATE
0.01 µF
GND
EACH CHANNEL
Figure 11. Recommended Logic Interface.
V
CC
V
D.U.T.*
OC
V
CC
(EACH INPUT)
–
0.1 µF
+
V
O
V
IN
(EACH OUTPUT)
GND
NOMINAL CONDITIONS
PER CHANNEL: I = 20 mA
F
I
I
= 4 mA
O
= 30 µA
CC
NOTE: BASE LEAD NOT CONNECTED.
= +125 °C
T
A
Figure 12. Operating Circuit for Burn-In and Steady State
Life Tests. All Channels Tested Simultaneously.
1-569
HP [ HEWLETT-PACKARD ]
