ATF-501P8 Absolute Maximum Ratings
[1]
Symbol
V
DS
V
GS
V
GD
I
DS
I
GS
P
diss
P
in max.
T
CH
T
STG
θ
ch_b
Parameter
Drain–Source Voltage
[2]
Gate–Source Voltage
[2]
Gate Drain Voltage
[2]
Drain Current
[2]
Gate Current
Total Power Dissipation
[3]
RF Input Power
Channel Temperature
Storage Temperature
Thermal Resistance
[4]
Units
V
V
V
A
mA
W
dBm
°C
°C
°C/W
Absolute
Maximum
7
-5 to 0.8
-5 to 1
1
12
3.5
30
150
-65 to 150
23
Notes:
1. Operation of this device in excess of any one
of these parameters may cause permanent
damage.
2. Assumes DC quiescent conditions.
3. Board (package belly) temperatureT
B
is 25°C.
Derate 43.5 mW/°C for T
B
> 69.5°C.
4. Channel-to-board thermal resistance
measured using 150°C Liquid Crystal
Measurement method.
Product Consistency Distribution Charts at 2 GHz, 4.5V, 200 mA
[5,6]
800
700
600
Ids (mA)
Vgs=0.7V
120
100
Vgs=0.65V
120
Cpk=1.76
Stdev=0.3
100
80
Cpk=1.51
Stdev=3.38
500
Vgs=0.6V
80
60
Vgs=0.55V
–3 Std
+3 Std
400
300
200
100
0
0
1
2
3
Vds (V)
4
5
6
60
40
20
0
45
–3 Std
+3 Std
40
Vgs=0.5V
20
0
27.5
28
28.5
29
29.5
30
30.5
55
65
PAE (%)
75
85
P1dB (dBm)
Figure 1. Typical IV curve
(Vgs = 0.01V) per step.
100
Figure 2. P1dB.
Figure 3. PAE.
100
Cpk=1.61
Stdev=0.33
80
80
Cpk=1.1
Stdev=0.87
60
60
–3 Std
40
+3 Std
40
–3 Std
+3 Std
20
20
0
13
14
15
GAIN (dB)
16
17
0
42
43
44
45
46
47
48
49
50
OIP3 (dBm)
Figure 4. Gain.
Figure 5. OIP3.
Notes:
5. Distribution data sample size is 300 samples taken from 3 different wafers and 3 different lots.
Future wafers allocated to this product may have nominal values anywhere between the upper and
lower limits.
6. Measurements are made on production test board, which represents a trade-off between optimal
OIP3, P1dB and VSWR. Circuit losses have been de-embedded from actual measurements.
2
HP [ AGILENT(HEWLETT-PACKARD) ]
