RFM23
Figure 17. Packet Structure
An overview of the packet handler configuration registers is shown in Table 14. A complete register description can
be found in ―12.1. Complete Register Table and Descriptions‖.
6.3. Packet Handler TX Mode
If the TX packet length is set the packet handler will send the number of bytes in the packet length field before returning to ready
mode and asserting the packet sent interrupt. To resume sending data from the FIFO the microcontroller needs to command the
module to re-enter TX mode Figure 18 provides an example transaction where the packet length is set to three bytes.
Figure 18. Multiple Packets in TX Packet Handler
6.4. Packet Handler RX Mode
6.4.1. Packet Handler Disabled
When the packet handler is disabled certain portions of the packet handler are still required. Proper modem operation requires
preamble and sync, as shown in Figure 19. Bits after sync will be treated as raw data with no qualification. This mode allows for
the creation of a custom packet handler when the automatic qualification parameters are not sufficient. Manchester encoding is
supported but the use of data whitening, CRC, or header checks is not.
Figure 19. Required RX Packet Structure with Packet Handler Disabled
6.4.2. Packet Handler Enabled
When the packet handler is enabled, all the fields of the packet structure need to be configured. If multiple packets are desired to
be stored in the FIFO, then there are options available for the different fields that will be stored into the FIFO. Figure 20
demonstrates the options and settings available when multiple packets are enabled. Figure 21 demonstrates the operation of
fixed packet length and correct/incorrect packets.
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