RFM22
6. Data Handling and Packet Handler
6.1. RX and TX FIFOs
Two 64 byte FIFOs are integrated into the module, one for RX and one for TX, as shown in Figure 10. "Register 7Fh.
FIFO Access" is used to access both FIFOs. A burst write, as described in "3.1. Serial Peripheral Interface (SPI)", to
address 7Fh will write data to the TX FIFO. A burst read from address 7Fh will read data from the RX FIFO.
Figure 16. FIFO Thresholds
The TX FIFO has two programmable thresholds. An interrupt event occurs when the data in the TX FIFO reaches
these thresholds. The first threshold is the FIFO Almost Full threshold, txafthr[5:0]. The value in this register
corresponds to the desired threshold value in number of bytes. When the data being filled into the TX FIFO
reaches this threshold limit, an interrupt to the microcontroller is generated so the module can enter TX mode to
transmit the contents of the TX FIFO. The second threshold for TX is the FIFO Almost Empty Threshold,
txaethr[5:0]. When the data being shifted out of the TX FIFO reaches the Almost Empty threshold an interrupt will
be generated. The microcontroller will need to switch out of TX mode or fill more data into the TX FIFO. The
Transceiver may be configured so that when the TX FIFO is empty the module will automatically move to the Ready
state. In this mode the TX FIFO Almost Empty Threshold may not be useful. This functionality is set by the ffidle bit
in ―Register 08h. Operating Mode and Function Control 2,‖.
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