RF42/43
Register 0Ah. Microcontroller Output Clock
Bit
D7
D6
D5
D4
D3
enlfc
R/w
D2
D1
mclk[2:0]
R/w
D0
Reserved
R
clkt[1:0]
R/w
Name
Type
Reset value = xx000110
Bit
Name
Function
Reserved
7:6
Reserved.
Clock Tail.
If enlfc = 0 then it can be useful to provide a few extra cycles for the
microcontroller to complete its operation. Setting the clkt[1:0] register will
provide the addition cycles of the clock before it shuts off.
5:4
clkt[1:0]
00:
01:
10:
11:
0 cycle
128 cycles
256 cycles
512 cycles
Enable Low Frequency Clock.
When enlfc = 1 and the chip is in Sleep mode then the 32.768 kHz clock will be
provided to the microcontroller no matter what the selection of mclk[2:0] is. For
example if mclk[2:0] = ‗000‘, 30 MHz will be available through the GPIO to
output to the microcontroller in all Idle or TX states. When the chip is
commanded to Sleep mode the 30 MHz clock will become 32.768 kHz.
Microcontroller Clock.
3
enlfc
Different clock frequencies may be selected for configurable GPIO clock
output. All clock frequencies are created by dividing the XTAL except for the 32
kHz clock which comes directly from the 32 kHz RC Oscillator. The mclk[2:0]
setting is only valid when xton = 1 except the 111.
000:
001:
010:
011:
100:
101:
110:
111:
30 MHz
15 MHz
10 MHz
4 MHz
2:0
mclk[2:0]
3 MHz
2 MHz
1 MHz
32.768 kHz
65
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