RF42/43
Figure 2. SPI Timing—READ Mode
The SPI interface contains a burst read/write mode which will allows for reading/writing sequential registers
without having to re-send the SPI address. When the nSEL bit is held low while continuing to send SCLK pulses,
the SPI interface will automatically increment the ADDR and read from/write to the next address. An SPI burst
write transaction is demonstrated in Figure 3 and burst read in Figure 2. As long as nSEL is held low, input data
will be latched into the RF42/43 every eight SCLK cycles. A burst read transaction is also demonstrated in Figure
4.
Figure 4. SPI Timing—Burst Read Mode
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