RF31
Register 04h. Interrupt/Status 2
Bit
D7
iswdet
R
D6
ipreaval
R
D5
ipreainval
R
D4
irssi
R
D3
iwut
R
D2
ilbd
R
D1
D0
ipor
R
ichiprdy
R
Name
Type
Reset value = xxxxxxxx
Function
Bit
Name
Sync Word Detected.
iswdet
7
When a sync word is detected this bit will be set to 1.
Valid Preamble Detected.
ipreaval
6
5
When a preamble is detected this bit will be set to 1.
Invalid Preamble Detected.
ipreainval
When the preamble is not found within a period of time set by the invalid
preamble detection threshold in Register 54h, this bit will be set to 1.
RSSI.
irssi
iwut
4
3
When RSSI level exceeds the programmed threshold this bit will be set to 1.
Wake-Up-Timer.
On the expiration of programmed wake-up timer this bit will be set to 1.
Low Battery Detect.
When a low battery event is been detected this bit will be set to 1. This interrupt
event is saved even if it is not enabled by the mask register bit and causes an
interrupt after it is enabled.
ilbd
2
Chip Ready (XTAL).
ichiprdy
ipor
1
0
When a chip ready event has been detected this bit will be set to 1.
Power-on-Reset (POR).
When the chip detects a Power on Reset above the desired setting this bit will
be set to 1.
When any of the Interrupt/Status Register 2 bits change state from 0 to 1 the control block will notify the
microcontroller by setting the nIRQ pin LOW if it is enabled in the Interrupt Enable 2 register. The nIRQ pin will go
to HIGH and all the enabled interrupt bits will be cleared when the microcontroller reads this address. If any of
these bits is not enabled in the Interrupt Enable 2 register then it becomes a status signal that can be read anytime
in the same location and will not be cleared by reading the register.
70
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