RF31
6. Data Handling and Packet Handler
6.1. RX FIFO
A 64 byte FIFO is integrated into the chip for RX, as shown in Figure 11. "Register 7Fh. FIFO Access" is used to
access the FIFO. A burst read, as described in "3.1. Serial Peripheral Interface (SPI)", from address 7Fh will read
data from the RX FIFO.
Figure 11. FIFO Threshold
POR
Def.
Function/Descri
ption
D7
D6
D5
D4
D3
D2
D1
D0
Add R/W
Operating &Function
Control 2
Reserved
antdi
v[2]
antdiv[1] antdiv[0] rxmpk Reserve enldm ffclrrx
d
R/W
00h
08
The RX FIFO has one programmable threshold called the FIFO Almost Full Threshold, rxafthr[5:0]. When the incoming RX
data reaches the Almost Full Threshold an interrupt will be generated to the microcontroller via the nIRQ pin. The
microcontroller will then need to read the data from the RX FIFO.
POR
Def.
Function/D
escription
RX FIFO
D7
D6
D5
D4
D3
D2
D1
D0
Add R/W
rxafthr rxafthr rxafthr rxafthr
[3] [2] [1] [0]
R/W
Reserved Reserved rxafthr[5] rxafthr[4]
37h
7E
Control
The RX FIFO may be cleared or reset with the ffclrrx bit in ―Register 08h. Operating Mode and Function Control 2,‖. All
interrupts may be enabled by setting the Interrupt Enabled bits in "Register 05h. Interrupt Enable 1" and ―Register 06h.
Interrupt Enable 2,‖. If the interrupts are not enabled the function will not generate an interrupt on the nIRQ pin but the bits
will still be read correctly in the Interrupt Status registers.
31
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