RF31
4. Modulation Options
4.1. FIFO Mode
In FIFO mode, the integrated FIFO is used to receive the data. The FIFO is accessed via "Register 7Fh. FIFO
Access" with burst read capability. The FIFO may be configured specific to the application packet size, etc. (see "6.
Data Handling and Packet Handler" for further information).
When in FIFO mode the chip will automatically exit the RX State when the ipkvalid interrupt occurs. The chip will
return to any of the other states based on the settings in "Register 07h. Operating Mode and Function Control 1".
In RX mode the rxon bit will only be cleared if ipkvalid occurs. A CRC, Header, or Sync error will generate an
interrupt and the microcontroller will need to decide on the next action.
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