HI-8282A
3. Each data bit must follow its predecessor by not less than
8 samples and no more than 12 samples. In this manner the
bit rate is checked. With exactly 1MHz input clock frequency,
the acceptable data bit rates are as follows:
FUNCTIONAL DESCRIPTION (cont.)
RECEIVER LOGIC OPERATION
Figure 2 shows a block diagram of the logic section of each re-
ceiver.
HIGH SPEED LOW SPEED
DATA BIT RATE MIN
DATA BIT RATE MAX
83K BPS
125K BPS
10.4K BPS
15.6K BPS
BIT TIMING
The ARINC 429 specification contains the following timing specifi-
cation for the received data:
4. The Word Gap timer samples the Null shift register every
10 input clocks (80 for low speed) after the last data bit of a
valid reception. If the Null is present, the Word Gap counter
is incremented. A count of 3 will enable the next reception.
HIGH SPEED
LOW SPEED
BIT RATE
100K BPS 1ꢀ 12K -14.5K BPS
RECEIVER PARITY
PULSE RISE TIME 1.5 0.5 µsec
PULSE FALL TIME 1.5 0.5 µsec
PULSE WIDTH
10 5 µsec
10 5 µsec
5 µsec 5ꢀ 34.5 to 41.7 µsec
The receiver parity circuit counts Ones received, including the
parity bit, ARINC bit 32. If the result is odd, then "0" will appear
in the 32nd bit.
The HI-8282A accepts signals that meet these specifications and
rejects outside the tolerances. The way the logic operation
achieves this is described below:
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates
an End of Sequence (EOS). If the receiver decoder is enabled
and the 9th and 10th ARINC bits match the control word pro-
gram bits or if the receiver decoder is disabled, then EOS clocks
the data ready flag flip flop to a "1", D/R1 or D/R2 (or both) will
go low. The data flag for a receiver will remain low until after
both ARINC bytes from that receiver are retrieved. This is ac-
complished by activating EN with SEL, the byte selector, low to
retrieve the first byte and activating EN with SEL high to retrieve
the second byte. EN1 retrieves data from receiver 1 and EN2 re-
trieves data from receiver 2.
1. Key to the performance of the timing checking logic is an ac-
curate 1MHz clock source. Less than 0.1ꢀ error is recom-
mended.
2. The sampling shift registers are 10 bits long and must show
three consecutive Ones, Zeros or Nulls to be considered valid
data. Additionally, for data bits, the One or Zero in the upper
bits of the sampling shift registers must be followed by a Null in
the lower bits within the data bit time. For a Null in the word
gap, three consecutive Nulls must be found in both the upper
and lower bits of the sampling shift register. In this manner the
minimum pulse width is guaranteed.
If another ARINC word is received and a new EOS occurs be-
fore the two bytes are retrieved, the data is overwritten by the
new word.
TO PINS
SEL
MUX
32 TO 16 DRIVER
CONTROL
CLOCK
OPTION
CONTROL
BIT BD14
CLK
EN
D/R
CLOCK
LATCH
ENABLE
CONTROL
DECODER
CONTROL
BITS
32 BIT LATCH
/
BIT
COUNTER
AND
END OF
SEQUENCE
BITS 9 & 10
32ND
BIT
DATA
PARITY
CHECK
32 BIT SHIFT REGISTER
BIT CLOCK
EOS
EOS
WORD GAP
TIMER
WORD GAP
ONES
NULL
SHIFT REGISTER
BIT CLOCK
END
START
SEQUENCE
CONTROL
SHIFT REGISTER
SHIFT REGISTER
ERROR
CLOCK
ZEROS
ERROR
DETECTION
FIGURE 2. RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
4
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
