HI-8282A
PIN DESCRIPTION
SYMBOL FUNCTION
DESCRIPTION
VCC
429DI1 (A)
429DI1 (B)
429DI2 (A)
429DI2 (B)
D/R1
POWER
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
I/O
+5V 5ꢀ
ARINC receiver 1 positive input
ARINC receiver 1 negative input
ARINC receiver 2 positive input
ARINC receiver 2 negative input
Receiver 1 data ready flag
D/R2
Receiver 2 data ready flag
SEL
Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)
EN1
Data Bus control, enables receiver 1 data to outputs
EN2
Data Bus control, enables receiver 2 data to outputs if EN1 is high
BD15
BD14
BD13
BD12
BD11
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
BD10
BD09
BD08
BD07
BD06
GND
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
POWER
I/O
0 V
BD05
BD04
BD03
BD02
BD01
BD00
PL1
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
I/O
Data Bus
INPUT
INPUT
Latch enable for byte 1 entered from data bus to transmitter FIFO.
Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1.
PL2
Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high
after transmission and FIFO empty.
TX/R
OUTPUT
429DO
429DO
ENTX
CWSTR
CLK
OUTPUT
OUTPUT
INPUT
"ONES" data output from transmitter.
"ZEROES" data output from transmitter.
Enable Transmission
INPUT
Clock for control word register
INPUT
Master Clock input
TX CLK
MR
OUTPUT
INPUT
Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.
Master Reset, active low
HOLT INTEGRATED CIRCUITS
2
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
