HI-3582, HI-3583
AC ELECTRICAL CHARACTERISTICS
VDD = 3.3V, V+=10V, V-=-10V, GND = 0V, TA = Oper. Temp. Range and fclk=1MHz +0.1% with 60/40 duty cycle
LIMITS
TYP
PARAMETER
SYMBOL
UNITS
MIN
MAX
CONTROL WORD TIMING
Pulse Width - CWSTR
Setup - DATA BUS Valid to CWSTR HIGH
Hold - CWSTR HIGH to DATA BUS Hi-Z
tCWSTR
tCWSET
tCWHLD
50
100
40
ns
ns
ns
RECEIVER FIFO AND LABEL READ TIMING
Delay - Start ARINC 32nd Bit to D/R LOW: High Speed
Low Speed
tD/R
tD/R
16
128
µs
µs
Delay - D/R LOW to EN LOW
Delay - EN HIGH to D/R HIGH
tD/REN
tEND/R
0
ns
ns
420
520
Setup - SEL to EN LOW
Hold - SEL to EN HIGH
tSELEN
tENSEL
10
10
ns
ns
Delay - EN LOW to DATA BUS Valid
Delay - EN HIGH to DATA BUS Hi-Z
tENDATA
tDATAEN
235
80
ns
ns
Pulse Width - EN1 or EN2
Spacing - EN HIGH to next EN LOW (Same ARINC Word)
Spacing -EN HIGH to next EN LOW (Next ARINC Word)
tEN
tENEN
tREADEN
60
65
200
ns
ns
ns
TRANSMITTER FIFO AND LABEL WRITE TIMING
Pulse Width - PL1 or PL2
tPL
120
ns
Setup - DATA BUS Valid to PL HIGH
Hold - PL HIGH to DATA BUS Hi-Z
tDWSET
tDWHLD
190
70
ns
ns
Spacing - PL1 or PL2
Spacing between Label Write pulses
tPL12
tLABEL
110
150
ns
ns
Delay - PL2 HIGH to TX/R LOW
Delay - PL2 HIGH to HFT low
tTX/R
240
560
ns
ns
tHFT
TRANSMISSION TIMING
Spacing - PL2 HIGH to ENTX HIGH
Delay - 32nd ARINC Bit to TX/R HIGH
Spacing - TX/R HIGH to ENTX LOW
tPL2EN
tDTX/R
0
0
ns
ns
ns
50
tENTX/R
LINE DRIVER OUTPUT TIMING
Delay - ENTX HIGH to TXAOUT or TXBOUT: High Speed
Delay - ENTX HIGH to TXAOUT or TXBOUT: Low Speed
tENDAT
tENDAT
25
200
µs
µs
Line driver transition differential times:
(High Speed, control register CR13 = Logic 0)
high to low
low to high
tfx
trx
1.0
1.0
1.5
1.5
2.0
2.0
µs
µs
(Low Speed, control register CR13 = Logic 1)
high to low
low to high
tfx
trx
5.0
5.0
10
10
15
15
µs
µs
REPEATER OPERATION TIMING
Delay - EN LOW to PL LOW
Hold - PL HIGH to EN HIGH
tENPL
tPLEN
tTX/REN
tMR
0
0
ns
ns
ns
ns
Delay - TX/R LOW to ENTX HIGH
0
MASTER RESET PULSE WIDTH
175
ARINC DATA RATE AND BIT TIMING
1%
HOLT INTEGRATED CIRCUITS
14