HI-3210
Example 2. ARINC 429 Data reception using on-chip filters and FIFOs
FILTER
TABLE 0
32 x 32 FIFO
8 x ARINC 429
Receive Buses
LABEL
FILTER
RECEIVER 0
HCSB
HSCLK
HMOSI
HMISO
SPI
FIFO STATUS
Host CPU
FIFO EMPTY
AINT
ARINC 429
FIFO THRESHOLD
FIFO FULL
RECEIVE FIFO
INTERRUPT
CONTROL
AACK
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
HI-3210
Example 3. ARINC 429 Data transmission directly from CPU
TRANSMITTER 0
TRANSMITTER 1
HCSB
HSCLK
HMOSI
HMISO
4 x ARINC 429
Transmit Buses
Host CPU
SPI
TRANSMITTER 2
TRANSMITTER 3
HI-3210
Example 4. ARINC 429 Data transmission using on-chip schedulers
TRANSMIT
SCHEDULER 0
Descriptor Table 0
Descriptor Table 1
Descriptor Table 2
TRANSMITTER 0
HCSB
HSCLK
HMOSI
HMISO
4 x ARINC 429
Transmit Buses
Host CPU
SPI
TRANSMIT TIMER
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
ECSB
ESCLK
EMOSI
EMISO
EEPROM
SPI
Auto-Initialization
EEPROM
Descriptor Table 3
RAM
HI-3210
HOLT INTEGRATED CIRCUITS
4
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
